Andrew Waterman
5f3fb64ef0
Per ABI, only x1 and x5 should be treated as function returns
...
We were doing so for x3 and x7, as well, which could reduce performance
for compilers that happen to perform indirect jumps via t2 (x7).
2016-11-22 12:01:05 -08:00
Wesley W. Terpstra
5fe107bb07
rocket: pass scratchpad address to block dcache
2016-11-21 21:13:26 -08:00
Wesley W. Terpstra
c18bc07bbc
TLB: determine RWX from TL2 properties directly
2016-11-21 21:13:26 -08:00
Henry Cook
28c6be90ab
[rocket] require refillcycesperbeat == 1 and remove flowthroughserializer
2016-11-20 19:36:51 -08:00
Henry Cook
ff9b5bf8fc
[rocket] nbdcache release bugfix
2016-11-20 19:07:06 -08:00
Henry Cook
3f47d5b5eb
[rocket] re-enable working NBDcache (passes Tracegen)
2016-11-19 19:19:16 -08:00
Colin Schmidt
9dd12545d0
[Rocket] Send correct type for iomshr reqs
...
Also contain grow param bugfix
2016-11-19 19:04:06 -08:00
Wesley W. Terpstra
32a1c27441
rocket: disable nbdcache until it's fully ported
2016-11-18 19:55:24 -08:00
Wesley W. Terpstra
452bb2fc80
dcache fix TinyConfig
2016-11-18 19:50:34 -08:00
Henry Cook
2976fd84e4
[rocket] resolve cde/config conflicts
2016-11-18 19:11:34 -08:00
Henry Cook
8b908465e0
[tl2] convert NBDcache to TL2 (WIP; compiles but untested)
2016-11-18 19:04:06 -08:00
Wesley W. Terpstra
37a3c22639
rocketchip: move from using cde to config
2016-11-18 16:18:33 -08:00
Wesley W. Terpstra
30425d1665
rocketchip: eliminate all Knobs
2016-11-18 14:31:42 -08:00
Henry Cook
5bd343bac8
[rocket] d_last && d.fire() => d_done
2016-11-17 18:42:59 -08:00
Henry Cook
1ddccb1b33
[rocket] add TODO for single cycle ack
2016-11-17 18:42:59 -08:00
Henry Cook
e1992d7c55
[rocket] grant addr bugfix
2016-11-16 18:12:06 -08:00
Henry Cook
da7ecfd189
[rocket] probeack vs probeackdata bugfix
2016-11-16 17:27:02 -08:00
Henry Cook
1f51564577
[rocket] dcache probe ack data bugfix
2016-11-16 14:25:21 -08:00
Henry Cook
66a2c5544e
[rocket] L1D acquire addr bugfix
2016-11-16 13:38:52 -08:00
Henry Cook
c5e03c9c76
[rocket] dcache release addr bugfix
2016-11-16 13:14:51 -08:00
Wesley W. Terpstra
10e459fedb
rocket: change connection between rocketchip and coreplex
...
* rtc and dtm are now crossed half-and-half on the two sides
* groundtest no longer uses riscv platform traits
2016-11-15 18:27:52 -08:00
Henry Cook
0e30364f56
WIP
2016-11-14 13:39:01 -08:00
Henry Cook
c0efd247b0
[tl2] expand firstlast api and L1WB bugfix
2016-11-14 12:12:31 -08:00
Henry Cook
b7730d66f2
WIP bugfixes: run until corrupted WB data (beats repeated)
2016-11-11 18:34:48 -08:00
Henry Cook
71315d5cf5
WIP scala compile and firrtl elaborate; monitor error
2016-11-11 13:07:45 -08:00
Henry Cook
afa1a6d549
WIP uncore and rocket changes compile
2016-11-10 15:57:29 -08:00
Wesley W. Terpstra
92ee498521
rocket scratchpad: support atomics
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
0cc00e7616
regressions: test scratchpad
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
545154c1c3
groundtest: make it happy with TL2 addressing
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
e9725aea2f
rocketchip: all of the address map now comes from TL2
2016-10-31 11:42:44 -07:00
Wesley W. Terpstra
b68bc449e7
rocket: put a Fragmenter infront of the scratchpad
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
825c253a72
rocketchip: move TL2 and cake pattern into Coreplex
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
11121b6f4c
rocket: convert scratchpad to TL2
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
dddb50a942
BuildTiles: convert to LazyTile
2016-10-31 11:42:13 -07:00
Colin Schmidt
85f3788ab5
initialize s2_hit to solve #401
2016-10-21 14:53:55 -07:00
Andrew Waterman
c22438b822
Fix an overly strict D$ assertion
2016-10-06 15:52:46 -07:00
Andrew Waterman
5980dc160f
Don't allow multiple entries for same PC in BTB
...
Necessary for RVC forward-progress guarantee.
2016-10-06 11:30:45 -07:00
Andrew Waterman
eddf1679f5
Use <> instead of := for bi-directional connections
2016-10-04 22:29:39 -07:00
Andrew Waterman
67593fdf2d
Explicitly zap some S-mode CSRs when not using S-mode
2016-10-04 22:29:39 -07:00
Andrew Waterman
064c9ebdc6
Don't report I$ fetch faults on TLB misses!
2016-10-04 14:37:25 -07:00
Andrew Waterman
516481b68b
Improve back-to-back integer multiplication performance
...
More exact hazard checking in the decode stage avoids a pipeline flush.
2016-10-04 14:37:25 -07:00
Andrew Waterman
7b69f1f261
Don't enter D$ flush state machine if grant outstanding
2016-10-04 14:37:25 -07:00
Andrew Waterman
28beb33943
Make any intervening load/store/fence fail an LR/SC sequence
...
This catches LR/SC misuses more quickly.
2016-10-04 14:37:25 -07:00
Andrew Waterman
e0188f8aa4
Don't implicitly fence on CSR instructions
...
CSRs that have an effect on I/O should use an explicit FENCE.
2016-10-01 19:44:10 -07:00
Andrew Waterman
b772edcb1b
Allow hit-under-MMIO and multiple MMIOs in blocking D$
...
The latter feature is by default disabled, since there aren't enough
ID bits.
2016-10-01 19:44:05 -07:00
Howard Mao
ab3219cf6e
don't use Scala to Chisel implicit conversions outside of rocket
2016-09-29 14:35:42 -07:00
Howard Mao
9910c69c67
Move a bunch more things into util package
...
A lot of utility code was just being imported willy-nilly from one
package to another. This moves the common code into util to make things
more sensible. The code moved were
* The AsyncQueue and AsyncDecoupledCrossing from junctions.
* All of the code in rocket's util.scala
* The BlackBox asynchronous reset registers from uncore.tilelink2
* The implicit definitions from uncore.util
2016-09-29 14:23:42 -07:00
Yunsup Lee
5bb575ef74
rename internal/external MMIO network to cbus/pbus respectively
2016-09-21 18:29:28 -07:00
Yunsup Lee
7afd630d3e
add multiclock support to Coreplex
2016-09-21 16:55:26 -07:00
Andrew Waterman
d0572d6aab
Allow reset vector to be set dynamically
...
A chip's power-up sequence, or awake-from-sleep sequence, may wish to
set the reset PC based upon dynamic properties, e.g., the settings of
external pins. Support this by passing the reset vector to the Coreplex.
ExampleTop simply hard-wires the reset vector, as was the case before.
Additionally, allow MTVEC to *not* be reset. In most cases, including
riscv-tests, pk, and bbl, overriding MTVEC is one of the first things
that the boot sequence does. So the reset value is superfluous.
2016-09-19 17:18:03 -07:00