Rimas Avizienis
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80b4253318
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fixed dcache amo bug, cleaned up testharness, added RDTIME instruction
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2011-11-16 02:04:28 -08:00 |
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Rimas Avizienis
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82a636ff55
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AMOADD, AMOAND, AMOOR, AMOSWAP working
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2011-11-15 00:51:45 -08:00 |
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Rimas Avizienis
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48cec01710
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updated riscv-bmarks and riscv-tests to build with new toolchain
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2011-11-15 00:11:22 -08:00 |
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Rimas Avizienis
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9d3471a569
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more cache fixes, more test harness debug output
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2011-11-13 23:32:18 -08:00 |
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Rimas Avizienis
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67c7e7e28f
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cache/tlb bugfixes, increased memory size to 256meg
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2011-11-13 13:06:35 -08:00 |
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Rimas Avizienis
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5f4b15b809
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added ld/st misaligned exceptions
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2011-11-13 00:03:17 -08:00 |
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Rimas Avizienis
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35af912bd2
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cache optimizations, cleanup, and testharness improvement
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2011-11-12 22:13:29 -08:00 |
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Rimas Avizienis
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91c252ad08
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fixing output enable signals for data/tag SRAMs
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2011-11-12 15:47:47 -08:00 |
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Rimas Avizienis
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83d90c4dab
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more itlb/dtlb/ptw fixes
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2011-11-12 15:00:45 -08:00 |
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Rimas Avizienis
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73416f224b
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more tlb/ptw debugging
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2011-11-12 00:25:06 -08:00 |
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Rimas Avizienis
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a1ce908541
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dcache/dtlb overhaul
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2011-11-11 18:18:47 -08:00 |
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Rimas Avizienis
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f86d5b1334
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cleanup, lots of minor fixes, added more PCR regs (COREID, NUMCORES), parameterized BTB
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2011-11-10 11:26:13 -08:00 |
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Rimas Avizienis
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9aca403aa8
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more itlb integration & cleanup
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2011-11-09 23:18:14 -08:00 |
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Rimas Avizienis
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e96430d862
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integrating ITLB & PTW
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2011-11-09 14:52:17 -08:00 |
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Rimas Avizienis
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9d63087eb2
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changed caches to use separate sram modules for tag and data arrays
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2011-11-07 00:58:25 -08:00 |
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Rimas Avizienis
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4d64099103
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cleanup
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2011-11-04 20:52:21 -07:00 |
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Rimas Avizienis
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4459935554
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dcache fixes - all tests and ubmarks pass, hello world still broken
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2011-11-04 15:40:41 -07:00 |
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Rimas Avizienis
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7a528d6255
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fixes for div/mul hazard checking + cleanup
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2011-11-01 23:14:34 -07:00 |
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Rimas Avizienis
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3b3d988fde
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dcache loads working - 1/2 cycle load/use delay depending on load type
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2011-11-01 21:25:52 -07:00 |
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Rimas Avizienis
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08b89e7710
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interface cleanup, major pipeline changes
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2011-11-01 17:59:27 -07:00 |
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Rimas Avizienis
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ace4c9d13c
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dcache fixes
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2011-10-31 17:17:36 -07:00 |
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Rimas Avizienis
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65f8b2461c
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dcache tweaks
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2011-10-31 16:47:31 -07:00 |
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Rimas Avizienis
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172e561a78
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added once cycle latency store pipelined d$
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2011-10-31 15:37:37 -07:00 |
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Rimas Avizienis
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c06e2d16e4
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initial commit of rocket chisel project, riscv assembly tests and benchmarks
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2011-10-25 23:02:47 -07:00 |
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