riscv/rocket-chip
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59eb7c24ee
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1049 Commits

Author SHA1 Message Date
Jacob Chang
59eb7c24ee Add iterator function to LazyModule to iterate over all nodes 2017-01-12 15:21:10 -08:00
Andrew Waterman
71c4b000b3 Don't special-case power-of-2 replacement policy for BTB 
PLRU wasn't implemented correctly for the BTB, since it wasn't
increasing the priority on replacement, only on usage.  Regardless,
this should be a second-order effect, so using FIFO always is fine.
 2017-01-11 13:21:55 -08:00
Jacob Chang
c531093898 Fix bug introduced with Fuzzer when nOperations is power of 2 (#492) 2016-12-15 19:10:53 -08:00
Wesley W. Terpstra
a9b264e582 ahb: lower hsel when idle to save power 2016-12-15 15:32:30 -08:00
Wesley W. Terpstra
16febe7e94 apb: add a TileLink to APB bridge and unittest it 2016-12-15 15:32:27 -08:00
Wesley W. Terpstra
ed091f55e6 apb: diplomatic APB framework 2016-12-15 13:48:50 -08:00
Wesley W. Terpstra
a5b8fc2317 RegisterRouterTest: start up with 0 in registers to make VIP testing easier 2016-12-14 15:38:08 -08:00
Wesley W. Terpstra
9d50704b64 ahb: don't violate spec with SRAM fuzzing 2016-12-14 15:18:41 -08:00
Jacob Chang
2dd9e522a0 Merge branch 'master' into jchang_test 2016-12-12 20:02:53 -08:00
Henry Cook
540502f96d Convert frontend and icache to diplomacy/tl2 (#486) 
* [rocket] file capitalization

* [rocket] cacheDataBits &etc in HasCoreParameters

* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters

* [rocket] frontend and icache now diplomatic
 2016-12-12 17:38:55 -08:00
Jacob Chang
531f3684ed Removing module list for merging. (will need to create iterator in future) 2016-12-12 16:25:31 -08:00
Jacob Chang
aae9b23036 Update with paratermized LazyModule 2016-12-12 16:16:56 -08:00
Jacob Chang
762afcd54a Merge remote-tracking branch 'origin/master' into jchang_test 2016-12-09 16:56:49 -08:00
Jacob Chang
4c3083c181 Remove unnecessary val 2016-12-09 16:44:30 -08:00
Wesley W. Terpstra
09afbbafdb ahb: weaken RegisterRouter assertion 
As written I think it could potentially fail, but what I actually care
about is something weaker that should be true. Assert: nothing lost.
 2016-12-08 18:00:39 -08:00
Wesley W. Terpstra
588b944ed4 ahb: implement and test address decoding 2016-12-08 18:00:39 -08:00
Wesley W. Terpstra
5d1064fcb1 ahb: include a unit test 2016-12-08 18:00:39 -08:00
Wesley W. Terpstra
51dfb9cb06 ahb: TileLink master 2016-12-08 18:00:39 -08:00
Wesley W. Terpstra
01b0f6a52b ahb: new diplomacy-based AHB bus definition 2016-12-08 18:00:39 -08:00
Jacob Chang
54cc071a64 Fix Fragmenter to ensure logical operations must be sent out atomically. 
Edited Fuzzer so that it can generate infinite operations when nOperations is net to 0
 2016-12-07 16:22:05 -08:00
Wesley W. Terpstra
c2eedbfe23 tilelink2 Monitor: use Parameters instead of global variables 2016-12-07 12:24:03 -08:00
Wesley W. Terpstra
020fbe8be9 diplomacy: make config.Parameters available in bundle connect() 
This makes it posisble to use Parameters to control Monitors.
However, we need to make all LazyModules carry Parameters.
 2016-12-07 12:24:01 -08:00
Andrew Waterman
915697cb09 Fix FEQ flag generation (#479) 
FEQ is not a signaling comparison (i.e., qNaN is not an invalid input).

Also, minor code cleanup.
 2016-12-06 11:54:29 -08:00
Wesley W. Terpstra
fbfa15efea TLBroadcast: support non-FIFO devices (#482) 2016-12-05 22:10:37 -08:00
Wesley W. Terpstra
3c9718ec8f clint: undefined registers must be zero (#480) 
This is needed so that SMP-safe boot loaders can safely
read/write to the IPI register of non-existent harts.
 2016-12-05 17:11:53 -08:00
Henry Cook
f3d0692619 Make a directory for the config package (#464) 
* [config] make dir structure mirror packages

* [config] expunge max_int
 2016-12-05 10:42:16 -08:00
Henry Cook
d0a0c887dc [tracegen] decrease default address bag size (#462) 
while increasing the default number of requests.
 2016-12-04 22:46:55 -08:00
Schuyler Eldridge
36fe024671 CacheName no longer needed in RoCCInterface 
With dcacheParams passed to a RoCC, the CacheName no longer needs to be
specified.
 2016-12-04 19:01:39 -08:00
Schuyler Eldridge
624db2034b Make instantiated RoCC use dcacheParams 2016-12-04 19:01:39 -08:00
Jacob Chang
cff2612cdb minor Changes needed to support formal tests 2016-12-01 15:02:23 -08:00
Wesley W. Terpstra
b7963eca4e copyright: ran scripts/modify-copyright 2016-11-27 22:15:43 -08:00
Wesley W. Terpstra
e2ec1d00ad copyright: normalize /// to // in comments 2016-11-27 22:15:43 -08:00
Wesley W. Terpstra
a0e10aec05 uncore: removed obsolete Builder file 2016-11-27 22:15:43 -08:00
Wesley W. Terpstra
4146f6a792 TLB: do not access illegal addresses (#460) 2016-11-26 15:11:42 -08:00
Wesley W. Terpstra
a17753983a coreplex: allow legacy devices to override the config string (#458) 2016-11-25 19:38:24 -08:00
Wesley W. Terpstra
233280e7d2 AsyncBundle: save a wasted bit when depth=1 2016-11-25 18:11:01 -08:00
Wesley W. Terpstra
d755edffcc DebugTransport: use ToAsyncDebugBus for correct depth 2016-11-25 18:10:28 -08:00
Wesley W. Terpstra
2b80386a9e rocketchip: TileInterrupts needs a TLCacheEdge (#456) 2016-11-25 17:02:29 -08:00
Wesley W. Terpstra
1e0aca7358 dcache: the high bit of s2_req.typ is the SIGN bit (not size) (#455) 2016-11-25 15:26:22 -08:00
Wesley W. Terpstra
0baa1c9a45 coreplex: CacheBlockOffsetBits was wrong! 
This bug is ancient. I don't understand how it never mattered before.
Anyway, in processors with a custom CacheBlockBytes, this value is wrong!
The symptom is that TL1 components end up missing high address bits.
This causes, for example, a system to jump to 0 instead of RAM.

I don't understand how this very serious bug did not cause problems before.
 2016-11-24 18:32:44 -08:00
Wesley W. Terpstra
a670f63c81 periphery: a handy trait to turn-off ExtMem 2016-11-23 20:44:45 -08:00
Wesley W. Terpstra
30e890b480 diplomacy: include InternalNodes for AXI4 and TL 2016-11-23 20:44:45 -08:00
Wesley W. Terpstra
9f1c668c4f config: when modifying Parameters, subordinate lookups use top 2016-11-23 20:44:45 -08:00
Wesley W. Terpstra
566cc9e60b rocketchip: RTCPeriod config 2016-11-23 20:44:45 -08:00
Wesley W. Terpstra
e87f54d4f7 rocketchip: traits for adding external TL2 ports 2016-11-23 20:44:42 -08:00
Wesley W. Terpstra
4b9dc78951 rocketchip: add a parameter-controlled debug port 2016-11-23 15:35:53 -08:00
Henry Cook
38c5af5bad [rocket] cleanup mshr logic 2016-11-23 12:09:56 -08:00
Henry Cook
dae6772624 factor out common cache subcomponents into uncore.util 2016-11-23 12:09:35 -08:00
Henry Cook
c65c255815 [coreplex] TileId moved to groundtest 2016-11-23 12:08:45 -08:00
Wesley W. Terpstra
1d3cad3671 tilelink2 SourceShrinker: handle degenerate cases for free 2016-11-22 22:17:30 -08:00