riscv/rocket-chip
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35 Commits
Author SHA1 Message Date
Wesley W. Terpstra aabd17d935 rocketchip: must create bundles within Module scope 
1. Bundles be created after base class Module constructor runs
2. Bundles must be created before Module(...) runs

Solution: pass a bundle constructor to the cake base class

Require the constructor to take a parameter so people don't use it by
accident; they should get a type error.

Consistently name all the cake arguments with an _io, _coreplex, _outer,
so that they don't shadow the base class variables you should be using.
 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra 688e1bffdf rocketchip: pull rtcTick out of the coreplex 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra 5bca13ebdb rocketchip: use self-type constraints 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra d51b0b5c02 rocketchip: use self-type 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra ba529c3716 rocketchip: use TileLink2 interrupts 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra ac886026e6 rocketchip: reduce number of type parameters 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra 72a7948ad2 rocketchip Periphery: move atomics before WidthWidget => 64-bit AMOs 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra e9725aea2f rocketchip: all of the address map now comes from TL2 2016-10-31 11:42:44 -07:00
Wesley W. Terpstra 401fd378b4 rocketchip: include devices from cbus in ConfigString 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra a73aa351ca rocketchip: fix all clock crossings 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra 825c253a72 rocketchip: move TL2 and cake pattern into Coreplex 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra c3dacca39a rocketchip: remove pbus; TL2 has swallowed it completely 2016-10-31 11:42:08 -07:00
Wesley W. Terpstra ec2d23b8b7 rocketchip: Bundle-slices need access to the outer LazyModule 
We need this change in order for some ports to use parameters that result
from LazyModule diplomacy.

Now you can eat your cake too!
 2016-10-31 11:41:18 -07:00
Wesley W. Terpstra 0ae45d0f24 rocketchip: bundle (=> B) need not be delayed; Module is constructed later 2016-10-31 11:41:18 -07:00
Wesley W. Terpstra 0dbda2f07d rocketchip: remove obsolete pDevices used during TL1=>2 migration 2016-10-31 11:41:18 -07:00
Wesley W. Terpstra 7dc97674d6 rocketchip: include an socBus between l1tol2 and periphery (#415) 
Sometimes we have high performance devices that go inbetween.
 2016-10-24 23:56:09 -07:00
Henry Cook 1e69a2dc1c [tilelink2] allow TL monitors to be globally enabled or disabled (#392) 2016-10-09 12:34:10 -07:00
Wesley W. Terpstra f05298d9bc tilelink2: move general-purpose code out of tilelink2 package 2016-10-03 16:22:28 -07:00
Wesley W. Terpstra 0a4ef66894 BaseTop: record top module; more general than GraphML 2016-10-03 15:05:45 -07:00
Howard Mao 9910c69c67 Move a bunch more things into util package 
A lot of utility code was just being imported willy-nilly from one
package to another. This moves the common code into util to make things
more sensible. The code moved were

 * The AsyncQueue and AsyncDecoupledCrossing from junctions.
 * All of the code in rocket's util.scala
 * The BlackBox asynchronous reset registers from uncore.tilelink2
 * The implicit definitions from uncore.util
 2016-09-29 14:23:42 -07:00
Yunsup Lee 0924f8adb0 print out assigned inerrupt ranges 2016-09-29 11:59:32 -07:00
Howard Mao 201e247f73 Factor coreplex IO connection into separate trait (#350) 
This would allow, for instance, putting the coreplex on a separate clock
domain and crossing the IOs over through asynchronous queues.

The ExampleMultiClockTop* classes are removed since they no longer fit
into the class hierarchy.
 2016-09-27 11:55:32 -07:00
Wesley W. Terpstra dd9558f45d rocketchip: generate GraphML output 2016-09-26 14:35:46 -07:00
Wesley W. Terpstra d175bb314d Periphery: make bus width and arithmetic atomics configurable (#337) 2016-09-23 15:25:58 -07:00
Wesley W. Terpstra a421469754 tilelink2: change adapters to use TLAdapter(params, defaults)(node) 
This API makes it much more readable when you have multiple adapters
combined into a single line. The arguments for each adapter stay
beside the adapter.

For example, this:
  peripheryBus.node := TLWidthWidget(TLBuffer(TLAtomicAutomata()(TLHintHandler(legacy.node))), legacy.tlDataBytes)
becomes this:
  peripheryBus.node := TLWidthWidget(legacy.tlDataBytes)(TLBuffer()(TLAtomicAutomata()(TLHintHandler()(legacy.node))))
 2016-09-22 20:52:46 -07:00
Henry Cook 673efb400d Merge branch 'master' into unittest-config 2016-09-22 16:20:53 -07:00
Henry Cook 1e54820f8c Merge remote-tracking branch 'origin/master' into unittest-config 2016-09-22 16:03:51 -07:00
Wesley W. Terpstra 0a3718881f rocketchip: re-enable testing of atomics 2016-09-22 15:18:54 -07:00
Henry Cook 47c5d1a992 [WIP] Move RocketTestSuite generation into RocketchipGenerator 2016-09-22 14:31:45 -07:00
Yunsup Lee 1b1ef3be07 simplify base Coreplex bundle 2016-09-21 18:29:28 -07:00
Yunsup Lee 5bb575ef74 rename internal/external MMIO network to cbus/pbus respectively 2016-09-21 18:29:28 -07:00
Yunsup Lee 7afd630d3e add multiclock support to Coreplex 2016-09-21 16:55:26 -07:00
Henry Cook ed91e9a89b Merge remote-tracking branch 'origin' into testharness-refactor 2016-09-20 13:03:21 -07:00
Henry Cook df442ed82c [rocketchip] avoid pending merge conflict] 2016-09-19 13:24:01 -07:00
Henry Cook 7b8aa6c839 [rocketchip] split out Base and Example tops 2016-09-19 11:00:13 -07:00