91 lines
3.2 KiB
Scala
91 lines
3.2 KiB
Scala
// See LICENSE for license details.
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package rocketchip
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import Chisel._
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import cde.{Parameters, Field}
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import junctions._
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import uncore.tilelink._
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import uncore.tilelink2._
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import uncore.devices._
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import util.{ParameterizedBundle, ConfigStringOutput}
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import rocket._
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import rocket.Util._
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import coreplex._
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// the following parameters will be refactored properly with TL2
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case object GlobalAddrMap extends Field[AddrMap]
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case object ConfigString extends Field[String]
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case object NCoreplexExtClients extends Field[Int]
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/** Function for building Coreplex */
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case object BuildCoreplex extends Field[(Parameters, CoreplexConfig) => Coreplex]
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/** Base Top with no Periphery */
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abstract class BaseTop(q: Parameters) extends LazyModule {
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// the following variables will be refactored properly with TL2
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val pInterrupts = new RangeManager
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val pBusMasters = new RangeManager
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val pDevices = new ResourceManager[AddrMapEntry]
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// Add a peripheral bus
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val peripheryBus = LazyModule(new TLXbar)
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lazy val peripheryManagers = peripheryBus.node.edgesIn(0).manager.managers
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lazy val c = CoreplexConfig(
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nTiles = q(NTiles),
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nExtInterrupts = pInterrupts.sum,
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nSlaves = pBusMasters.sum,
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nMemChannels = q(NMemoryChannels),
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hasSupervisor = q(UseVM),
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hasExtMMIOPort = true
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)
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lazy val genGlobalAddrMap = GenerateGlobalAddrMap(q, pDevices.get, peripheryManagers)
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private val qWithMap = q.alterPartial({case GlobalAddrMap => genGlobalAddrMap})
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lazy val genConfigString = GenerateConfigString(qWithMap, c, pDevices.get, peripheryManagers)
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implicit val p = qWithMap.alterPartial({
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case ConfigString => genConfigString
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case NCoreplexExtClients => pBusMasters.sum})
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val legacy = LazyModule(new TLLegacy()(p.alterPartial({ case TLId => "L2toMMIO" })))
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peripheryBus.node := TLBuffer(TLWidthWidget(TLHintHandler(legacy.node), legacy.tlDataBytes))
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}
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class BaseTopBundle(val p: Parameters, val c: Coreplex) extends ParameterizedBundle()(p) {
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val success = Bool(OUTPUT)
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}
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abstract class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L, b: Coreplex => B) extends LazyModuleImp(l) {
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val outer: L = l
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val coreplex = p(BuildCoreplex)(p, outer.c)
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val io: B = b(coreplex)
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val mmioNetwork =
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Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).subMap("io:ext"))(
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p.alterPartial({ case TLId => "L2toMMIO" })))
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mmioNetwork.io.in.head <> coreplex.io.master.mmio.get
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outer.legacy.module.io.legacy <> mmioNetwork.port("TL2")
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println("Generated Address Map")
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for (entry <- p(GlobalAddrMap).flatten) {
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val name = entry.name
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val start = entry.region.start
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val end = entry.region.start + entry.region.size - 1
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val prot = entry.region.attr.prot
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val protStr = (if ((prot & AddrMapProt.R) > 0) "R" else "") +
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(if ((prot & AddrMapProt.W) > 0) "W" else "") +
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(if ((prot & AddrMapProt.X) > 0) "X" else "")
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val cacheable = if (entry.region.attr.cacheable) " [C]" else ""
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println(f"\t$name%s $start%x - $end%x, $protStr$cacheable")
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}
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println("Generated Configuration String")
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println(p(ConfigString))
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ConfigStringOutput.contents = Some(p(ConfigString))
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io.success := coreplex.io.success
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}
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