riscv/rocket-chip
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Author SHA1 Message Date
Megan WachsandWesley W. Terpstra f2002839eb TLFragmenter: Continuing my spot battles on requires without explanatory strings (#882) 2017-07-21 21:55:32 -07:00
Megan WachsandGitHub 35464782b5 PLIC: maxPriorities comes from params 2017-07-13 15:57:10 -07:00
Megan WachsandGitHub f646bed3ea PLIC: Use longer DTS name for Max Priorities. 
I used the singular because there is really only one max priority
 2017-07-13 13:37:22 -07:00
Megan WachsandGitHub 0800fd3ed9 PLIC: Add maxPri as well as ndev in DTS 2017-07-13 13:18:50 -07:00
Megan WachsandWesley W. Terpstra 177ccbb663 regfield: More explanatory requires so I don't have to RTFC and figure out what width actually was (#855) 2017-07-10 21:07:50 -07:00
Megan WachsandGitHub c28c23150d Merge pull request #850 from freechipsproject/plic_undefZero 
PLIC: (undefZero=true) Don't allow addresses to alias
 2017-07-06 18:39:10 -07:00
Megan WachsandGitHub 76a1ae667f PLIC: (undefZero=true) Don't allow addresses to alias 
While the spec is unclear what happens when you access unused registers in the PLIC, for user simplicity turn off register aliasing. If this becomes a performance/area issue we can revisit.
 2017-07-06 17:57:08 -07:00
Megan WachsandGitHub 988caf5e34 Merge pull request #848 from freechipsproject/revert-839-bump-firrtl 
Revert "Bump firrtl"
 2017-07-05 22:32:45 -07:00
Megan WachsandGitHub 029886d0d5 Revert "Bump firrtl" 2017-07-05 21:13:47 -07:00
Megan WachsandGitHub 734a178e4e Merge pull request #846 from freechipsproject/travis-delete-caches 
Update README_TRAVIS.md
 2017-07-05 13:52:26 -07:00
Megan WachsandGitHub 94262ea950 Update README_TRAVIS.md 
add some headers
 2017-07-05 11:45:04 -07:00
Megan WachsandGitHub 84c2bf5504 Update README_TRAVIS.md 
Clarify when to delete caches
 2017-07-05 11:40:36 -07:00
Megan WachsandGitHub 85f37146d5 Merge pull request #842 from freechipsproject/fesvr-multi 
Bump FESVR for multi-core support
 2017-07-03 15:31:41 -07:00
Megan Wachs ddd2b2236d bump riscv-tools/riscv-fesvr to pick up multicore fixes 2017-07-03 13:25:05 -07:00
Megan Wachs 3d28c0182d travis: add a branch whitelist with just 'master'. 
Travis allows us to build on branch updates and on PRs. Right now our process is to build always on PRs, but to manually only build 'master' when we know that riscv-tools has been bumped (because that rebuilds the master cache which holds riscv-tools). But this is an annoying and error-prone processes that requires extra admin permissions.

With this change, i think we can just leave "Build Branch Updates" to "ON" and get the same effect we are currently doing manually, because only on update to master branch will it do a build. PRs to master branch will get a build. PRs to other branches will I believe NOT get a build.
 2017-07-03 13:25:05 -07:00
Megan WachsandGitHub 69ab3626ca Merge pull request #837 from freechipsproject/plic_recode 
plic: Recode to use OH knowledge
 2017-06-30 16:05:32 -07:00
Megan WachsandGitHub 8c92c50d85 plic: make assertion comment right 2017-06-30 14:25:09 -07:00
Megan Wachs f31ae008f3 plic: Clean up comments and simplify checking 2017-06-30 14:15:26 -07:00
Megan Wachs 76f8de75e3 plic: comment tidying 2017-06-30 12:51:09 -07:00
Megan Wachs 3da26b0aa8 plic: Add some assertions to check one-hot assumptions 2017-06-30 12:32:58 -07:00
Megan WachsandGitHub 237689b799 Merge pull request #838 from freechipsproject/more_plic 
plic: Use same recoding technique on complete as well as claim
 2017-06-30 11:06:27 -07:00
Megan Wachs e8e709c941 plic: Use same recoding technique on complete as well as claim 2017-06-30 08:36:00 -07:00
Megan WachsandGitHub 834bcf6b7e PLIC: simplify some scala code 2017-06-29 19:35:15 -07:00
Megan Wachs eae4fe1469 plic: Recode to use the knowledge that only one interrupt can be claimed at a time. 2017-06-29 19:09:57 -07:00
Megan WachsandGitHub ae6971b6db Merge pull request #834 from freechipsproject/resumereq-race 
debug: Fix race between resumereq and resumeack
 2017-06-29 13:38:20 -07:00
Megan Wachs 0668f13d99 debug: Fix race between resumereq and resumeack 
For an arbitrary DMI master on a fast clock running against a core
on a slow clock, there was a race between writing resumereq and
reading resumeack. When using JTAG DTM this does not occur in practice,
but clean it up for running simulations with FESVR and future DMI masters.
 2017-06-29 12:27:23 -07:00
Megan WachsandGitHub 992b480c74 Merge pull request #825 from freechipsproject/debug_wfi 
Debug + WFI Interactions
 2017-06-28 21:28:51 -07:00
Megan Wachs 39b06a917f bump riscv-tools for fesvr-dont-die 2017-06-28 16:38:02 -07:00
Megan Wachs 35b89d8023 bump riscv-tools for fesvr-don't-die 2017-06-28 13:36:53 -07:00
Megan Wachs 3fc75c2714 debug: report UNSUPPORTED more consistently. Allow haltreq/resumereq to be R as well as W. 2017-06-27 17:40:58 -07:00
Megan Wachs e1fe0f245b debug: Don't reset debugint register, as none of the interrupt registers are. 2017-06-27 14:10:13 -07:00
Megan Wachs 136e4b6c27 debug: use consistent coding style (Reg(init ... ) vs RegInit) 2017-06-27 13:42:38 -07:00
Megan Wachs 3b9550ede3 debug: correctly declare reg_debugint 2017-06-27 13:42:38 -07:00
Megan Wachs 56839b2c62 debug: Remove DebugInterrupt from DCSR (it is no longer part of V13 spec) 2017-06-27 13:42:38 -07:00
Megan Wachs 665c2a349c Correct Debug + WFI Interactions 
1) Debug interrupt should end WFI
2) WFI should end immedately during single-step
3) WFI should act like NOP during Debug Mode
 2017-06-27 13:42:38 -07:00
Megan WachsandGitHub d0f8cdd00c Merge pull request #804 from freechipsproject/travis_cache_stages 
travis: attempt to make 2 build stages for cache
 2017-06-16 07:31:56 -07:00
Megan WachsandGitHub 30a3e3ef55 travis: attempt to make 2 build stages for cache 
First stage builds riscv-tools, next stage builds verilator
 2017-06-15 21:31:15 -07:00
Megan WachsandGitHub d316aeb275 Merge pull request #799 from freechipsproject/bump-riscv-tools-start-multiple-harts 
Bump riscv-tools to pick up FESVR which allows starting all harts
 2017-06-15 13:55:46 -07:00
Megan Wachs 9a789fc0cf Bump riscv-tools to pick up FESVR which allows starting all harts 2017-06-15 11:05:07 -07:00
Megan WachsandGitHub f0a59a81c8 Merge pull request #783 from freechipsproject/plusarg_docstring 
plusarg_reader : Add the ability to add a documentation string.
 2017-06-05 18:21:07 -07:00
Megan Wachs 8d2e9a8631 Merge remote-tracking branch 'origin/master' into plusarg_docstring 2017-06-05 17:23:44 -07:00
Megan WachsandGitHub 7afd5e6070 remove unnecessary whitespace. Fix grammar. 2017-06-05 16:18:57 -07:00
Megan Wachs 8440c4b1c4 plusarg_reader : Add the ability to add a documentation string. 2017-06-05 16:16:52 -07:00
Megan WachsandGitHub 8d04e0efb8 Merge pull request #771 from freechipsproject/jtag_vpi_tab 
JTAG VPI: Make it work without debug_pp flag
 2017-05-30 17:29:23 -07:00
Megan Wachs 6aa13b4e01 JTAG VPI: Make it work without debug_pp flag 2017-05-30 15:46:45 -07:00
Megan WachsandGitHub f61e30763f Merge pull request #768 from freechipsproject/flush_jtag_vpi 
jtag_vpi: Attempt to more aggressively flush the simulator output
 2017-05-26 15:51:43 -07:00
Megan Wachs 0493372027 jtag_vpi: Attempt to more aggressively flush the simulator output as it is needed by other listeners 2017-05-26 11:48:45 -07:00
Megan WachsandWesley W. Terpstra 24a533e77c debug: Bump riscv-tools to pick up correction in gdbserver 2017-05-18 18:46:46 -07:00
Megan WachsandWesley W. Terpstra 304e82486f Debug: Update makefile now that OpenOCD is part of riscv-tools 2017-05-18 18:46:46 -07:00
Megan WachsandWesley W. Terpstra 26194b3078 bump riscv-tools to pick up latest version of debug tests 2017-05-18 18:46:45 -07:00
Megan WachsandGitHub d8996ea85f Empty commit to force travis 2017-05-16 22:56:58 -07:00
Megan WachsandGitHub f8c92d2669 Merge branch 'master' into pipeline-mmio 2017-05-03 08:37:12 -07:00
Megan Wachs 922a8ef5e0 local_interrupts: Correct off-by-1 if there is no SEIP 2017-05-02 21:55:25 -07:00
Megan WachsandGitHub d67738204f Interrupts: Less Pessimistic Synchronization (#714) 
* interrupts: Less pessimistic synchronization for the different interrupt types. There are some issues with the interrupt number assignments.

* interrupts: Allow an option to NOT synchronize all the external interrupts coming into PLIC

* interrupts: ExampleRocketChipTop uses PeripheryAsyncExtInterrupts. Realized 'abstract' doesn't do what I thought in Scala.

* interrupts: use consistent async/periph/core ordering

* interrupts: Properly condition on 0 External interrupts

* interrupts: CLINT is also synchronous to periph clock
 2017-04-28 14:49:24 -07:00
Megan Wachs 7ad4cc36f7 debug: Prevent writes to DATA/PROGBUF when busy 2017-04-26 11:11:21 -07:00
Megan WachsandAndrew Waterman e9db531e81 point to riscv-tools README for dependencies (#705) 
As pointed out, if we just point to 'master' branch, then people wouldn't get the correct list of dependencies.
 2017-04-25 20:20:27 -07:00
Megan Wachs c72b15f2a0 Down with any require() statement that makes me RTFC 2017-04-21 15:44:42 -07:00
Megan Wachs 9002e7e532 debug: Debug Module needs to handle DMI NOPs even if DTM won't send them. 2017-04-20 10:19:50 -07:00
Megan Wachs cc7f0a5b7a debug: whitespace cleanup 2017-04-20 10:19:50 -07:00
Megan Wachs 5934779082 debug: Clean up ValidReg assertion. 2017-04-20 10:19:50 -07:00
Megan Wachs 0c013a56c0 debug: Make DMI NOPs really NOPs. 
This simplifies SW design and CDC issues.
 2017-04-20 10:19:50 -07:00
Megan Wachs 1be13d6b4c PLIC: To avoid hazard between enable -> claim, enforce concurrency=1 2017-04-19 21:37:37 -07:00
Megan Wachs 3dfd584075 regmapper: remove the Pipe in the RegMapper Queue 
With this pipe here, devices which declare concurrency > 0
actually accept transactions on the same cycle they complete
the previous one. This is unexpected behavior.
 2017-04-19 21:37:37 -07:00
Megan WachsandGitHub 408107447c debug: DMI response should be busy, not zero, when there is an error. (#685) 2017-04-18 21:41:52 -07:00
Megan WachsandYunsup Lee 9cf86fa105 debug: checkpoint pointing to riscv-tools that picks up some tweaks in the debug riscv-tests 2017-04-17 10:28:33 -07:00
Megan WachsandYunsup Lee 9a6e7afc93 debug: bump OpenOCD to latest version of newprogram (with Examined RISC-V core message) 2017-04-17 10:28:33 -07:00
Megan WachsandYunsup Lee af6b2d8051 debug: DATA Region has to be aligned for ld/sd to correctly detect 64-bit cores. 2017-04-17 10:28:33 -07:00
Megan WachsandYunsup Lee b44d5f9386 debug: correctly consider .transfer bit in COMMAND 2017-04-17 10:28:33 -07:00
Megan WachsandYunsup Lee 79477fbea6 debug: Properly consider 'transfer' bit 2017-04-17 10:28:33 -07:00
Megan WachsandYunsup Lee 2dc4be6294 debug: remove preexec. Simplify the state machine since you can always just 'execute' once. 2017-04-17 10:28:33 -07:00
Megan WachsandYunsup Lee c5cb8b714f debug: Bump version and location of OpenOCD to pick up fix for off-by-1 in hartsel 2017-04-17 10:28:33 -07:00
Megan WachsandAndrew Waterman fd7f4a4c0f jtag: make it easier to assign MFR ID externally 2017-04-14 01:03:11 -07:00
Megan WachsandAndrew Waterman bef88c4c30 Add pointers to package dependencies to README (#670) 
Tell people where to look to find package dependency information
 2017-04-11 19:54:46 -07:00
Megan WachsandAndrew Waterman 051acee76c Debug: Fix off-by-1 for detecting nonexistent harts. 2017-04-07 16:47:16 -07:00
Megan WachsandAndrew Waterman 01372e1686 use Wire() correctly to assign a value 2017-04-07 16:47:16 -07:00
Megan WachsandAndrew Waterman 9ae4838708 jtag: Get rid of chisel deprecation warnings 2017-04-07 16:47:16 -07:00
Megan WachsandAndrew Waterman 22c6f728c3 debug: Use flags for resume instead of program buffer. Untested. 2017-04-07 16:47:16 -07:00
Megan WachsandAndrew Waterman d361e9e343 debug: temporarily leave preexec in place 2017-04-07 16:47:16 -07:00
Megan WachsandAndrew Waterman 0e2c34b0d6 debug: update register map with new spec 2017-04-07 16:47:16 -07:00
Megan WachsandGitHub df5caba7bf debug: Make it easier to override parts of the Default Debug Config (#655) 
* Handle single-step with a pipeline stall, not a flush

The pipeline flush approach broke when I changed the pipeline stage
the flush happens from

* debug: Make it easier to override parts of the Default Debug Config

* Fix typo in Debug code generation

abstractGeneratedI should be abstractGeneratedS when pulling out the opcode.
This doesn't actually break anything, but fix it for clarity.
 2017-04-06 10:33:17 -07:00
Megan WachsandAndrew Waterman c5b0b6fb85 debug: bump openOCD version to pick up read_mem fix. Use MemTest64 instead because it's more likely to fail than SimpleS0Test 2017-04-05 15:14:32 -07:00
Megan WachsandAndrew Waterman 2601740542 debug: fix some typos related to the ID->SEL mapping functions 2017-04-05 15:14:32 -07:00
Megan WachsandAndrew Waterman b94f1f15b0 debug: redirect DMI NOPs to CONTROL register so things don't hang during reset 2017-04-05 15:14:32 -07:00
Megan WachsandAndrew Waterman eef05cc1fc debug: Enforce mapping between hartsel and hartid, use more reasonable defaults for DATA and PROGBUF sizes. 2017-04-05 15:14:32 -07:00
Megan WachsandGitHub 629e9a2ef6 debug: Put DebugROM back inside the overall Debug Module (#647) 2017-04-03 16:36:53 -07:00
Megan WachsandGitHub d2c1bdc2ce Debug Controls (#639) 
* debug: Bump OpenOCD version to one that drives resets and sets cmderr appropriately.

* debug: Export the dmactive and ndreset signals to the top level and drive reset as intended in the TestHarness.
 2017-04-03 13:31:35 -07:00
Megan Wachs dec567ab0c Resturn riscv-tools to the priv 1.10 branch vs the pre-merge Debug v013 version. 2017-03-30 20:22:54 -07:00
Megan Wachs 0828ebe911 debug_v013: bump fesvr to use autoexec feature for memory writes. 2017-03-30 11:46:28 -07:00
Megan Wachs 9de06f8c83 Merge remote-tracking branch 'origin/master' into debug_v013_pr 2017-03-30 08:01:11 -07:00
Megan Wachs a14b7b5794 debug_v013: bump riscv-tools for slightly more efficient FESVR 2017-03-29 21:42:36 -07:00
Megan Wachs 24509fc69f debug_v013: Bump FESVR to pick up minor off-by-1 in error printing code. 2017-03-29 15:20:07 -07:00
Megan Wachs d8033b20fc Merge remote-tracking branch 'origin/master' into debug_v013_pr 2017-03-29 14:58:04 -07:00
Megan Wachs f6e72a3ef6 debug: Bump riscv-tools to pick up FESVR to version that works with debug v013 2017-03-29 14:46:06 -07:00
Megan Wachs 375a039279 debug: Use proper write-1-to-clear ABSTRACTCS.cmderr behavior (because fesvr code is using correct spec) 2017-03-28 21:14:22 -07:00
Megan Wachs ca9a5a1cf7 debug: Fixes in how the SimDTM was hooked up to FESVR 2017-03-28 21:13:45 -07:00
Megan Wachs ff38ebdf5e debug: Bump FESVR version to initial Debug v13. Doesn't work yet. 2017-03-28 21:12:57 -07:00
Megan Wachs d6ab929c41 debug: Remove older version of JTAG interface as it is superseded by the one in jtag package. 2017-03-27 21:25:37 -07:00
Megan Wachs cbc8d2400a debug: remove old Verilog DebugTransportModuleJtag file as it has been replaced by Chisel version 2017-03-27 21:24:44 -07:00
Megan Wachs bb64c92906 csr: Bring functionality in line with v13 spec. ebreak does not cause exception in Debug Mode, it just starts at Debug ROM again. 2017-03-27 21:21:48 -07:00
Megan Wachs 42ca597478 debug: Breaking change until FESVR is updated as well. 
* Replace v11 Debug Module with v13 module.
* Correct all instantiating interfaces.
* Rename "Debug Bus" to "DMI" (Debug
  Module Interface)
* Use Diplomacy interrupts for DebugInterrupt
* Seperate device for TLDebugROM
 2017-03-27 21:19:08 -07:00