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Commit Graph

273 Commits

Author SHA1 Message Date
5566bf1b13 Don't route PLIC interrupts through PRCI
The PLIC is local to the Coreplex, and PRCI should not be.
2016-09-14 11:01:05 -07:00
7dd4492abb First cut at refactoring unittests into a top-level utility. Individual tests co-located with their DUT. No functional changes. 2016-09-13 20:30:14 -07:00
61cbe6164d Add option to execute JAL from decode stage
This is particularly helpful for designs that don't have a BTB, but
it becomes the critical path for designs with RVC.  Caveat emptor.
2016-09-13 02:32:00 -07:00
266a2f24bd Disable Mul early out by default if XLen == 32
With a default unroll of 8, it doesn't help performance, but costs area.
2016-09-12 16:50:08 -07:00
f3cdeb08c6 pass nMemChannels to coreplex through CoreplexConfig 2016-09-12 12:40:10 -07:00
bb3f514e8d now able to add periphery devices through traits
Unfortunately, I had to touch a lot of code, which weren't quite possible to split up into multiple commits.
This commit gets rid of the "extra" infrastructure to add periphery devices into Top.
2016-09-10 23:39:29 -07:00
254f49093c only use companion objects for types 2016-09-07 12:32:34 -07:00
70cfd7ce13 Make DefaultRV32Config be RV32IMAFCS, not RV32IMC
The latter is more the domain of TinyConfig.
2016-09-07 01:58:25 -07:00
9fea4c83da Add RV32F support 2016-09-07 00:05:39 -07:00
f34843f1b9 fix assignment of incoherent vector 2016-09-04 10:12:16 -07:00
a4c1942958 flatten Coreplex module hierarchy 2016-09-02 17:45:08 -07:00
63679bb019 Add support for L1 data scratchpads instead of caches
They fit in the same part of the address space as DRAM would be, and
are coherent (because they are not cacheable).

They are currently limited to single cores without DRAM.  We intend
to lift both restrictions, probably when we add support for
heterogeneous tiles.
2016-09-02 16:22:07 -07:00
fb50f7c9dd Set default TileLink width to XLen 2016-09-02 15:27:54 -07:00
6872000f5e Merge pull request #239 from ucb-bar/move_rtc
Move RTC
2016-09-02 15:17:49 -07:00
8163a6b597 Make it easier to override the 'placeholder' Real-Time-Clock, to allow more real-world applications 2016-09-02 11:11:40 -07:00
c05ba1e864 Add TileId parameter, generalizing GroundTestId
This usually shouldn't be used in Tiles that are meant to be P&R'd once
and multiply instantiated, as their RTL would no longer be homogeneous.
However, it is useful for conditionalizing RTL generation for
heterogeneous tiles.
2016-09-02 00:10:50 -07:00
f4524e4c91 Add PML for Boolean.option; use it 2016-08-31 13:43:04 -07:00
8dbee2b133 Don't conditionalize running bmarks on UseVM 2016-08-29 13:43:29 -07:00
f91552a650 Add performance counter support 2016-08-29 12:31:52 -07:00
9ca82dd397 reset default MulDiv config to moderately fast default
Closes #228.

In commit 3f8c60bbd6 I inadvertently
changed the configuration while refactoring it.
2016-08-29 12:31:52 -07:00
93c801f598 Streamline the Generator App and associated utilities. Remove deprecated call to chiselMain and useless Chisel2 args. Update arguments to sbt run. (#227) 2016-08-25 17:26:28 -07:00
22ffe36258 Add a queue for timing QoR between L2->MMIO network (#217) 2016-08-19 22:51:49 -07:00
7b20609d4d reorganize moving non-submodule packages into src/main/scala 2016-08-19 13:45:23 -07:00