riscv/rocket-chip
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1593 Commits

Author SHA1 Message Date
Wesley W. Terpstra
94f85e8bc8 tilelink2: TLMonitor will not create giant wires 2017-06-13 16:58:22 -07:00
Colin Schmidt
8264c0a77e add a debug print for xbar id mappings 2017-06-13 16:58:21 -07:00
Henry Cook
9bbde9767c rocketchip: top-level systems are now multi-IO modules 
Cake pattern only 2 layers instead of 3.
Standardized naming convention.
Comments for periphery mix-ins.
Testharnesses use new periphery helper methods.
 2017-06-13 13:55:45 -07:00
Henry Cook
2e8a40a23f diplomacy: Allow LazyModuleImps to be based on RawModules or MultiIOModules 
And add a MonitorBase class to be connect's return type.
 2017-06-13 13:55:27 -07:00
Andrew Waterman
76af15a6ff Fix FPU control bug for div/sqrt 
I was examining a WB-stage control signal instead of a MEM-stage control
signal.  I refactored the code to group the signals together, so that this
sort of bug is less likely going forward.
 2017-06-09 15:51:06 -07:00
Andrew Waterman
8552c77972 Fix I$ reset regression FU-357 
Can't rely on s2 TLB response, so mask using s2_valid.
 2017-06-09 00:48:24 -07:00
Andrew Waterman
5a4daebbcc minNum -> minimumNumber (#766) 2017-06-08 11:12:52 -07:00
Andrew Waterman
8cb250cfe6 Fix FMUL sign, again (#789) 2017-06-08 01:50:00 -07:00
Leway Colin
60c896b48c Typo: is should be if ? (#786) 
Typo: is should be if ?
 2017-06-07 10:40:13 -07:00
Andrew Waterman
d45fc0d670 Merge pull request #785 from freechipsproject/fmul-fix 
Fix FMUL sign of zero
 2017-06-06 00:46:03 -07:00
Andrew Waterman
07ad9203ff Fix FMUL sign of zero 2017-06-05 17:35:42 -07:00
Megan Wachs
8d2e9a8631 Merge remote-tracking branch 'origin/master' into plusarg_docstring 2017-06-05 17:23:44 -07:00
Wesley W. Terpstra
87a5665e43 axi4: only block writes if SAME master has outstanding reads (#782) 
* axi4: only block writes if SAME master has outstanding reads
* tilelink2: ToAXI4 rename variable
TL uses sources, not IDs like AXI. Keep it less confusing.
* tilelink2: ToAXI4 improve stall circuit delay
Don't bother decoding the AXI ID to compute stall.
 2017-06-05 16:54:00 -07:00
Megan Wachs
7afd5e6070 remove unnecessary whitespace. Fix grammar. 2017-06-05 16:18:57 -07:00
Megan Wachs
8440c4b1c4 plusarg_reader : Add the ability to add a documentation string. 2017-06-05 16:16:52 -07:00
solomatnikov
274d908d98 Changed TLXbar arbitration policy to roundRobin (#781) 2017-06-05 10:20:28 -07:00
Andrew Waterman
16ecbdd5b2 Reduce fanout on critical I$ miss signal 2017-06-02 20:45:50 -07:00
Andrew Waterman
27b143013f Improve ITLB QoR 
- No need to check cacheability
- Remove a gate delay from PMP path
 2017-06-02 20:45:50 -07:00
Andrew Waterman
0ffb2c8baf Simplify and improve QoR of ShiftQueue 2017-06-02 20:44:52 -07:00
Andrew Waterman
8229bdee03 Remove FP unboxing from FMA critical path 2017-06-02 20:44:52 -07:00
Andrew Waterman
7504b47bbe Improve code quality in FP->FP and Int->FP units 2017-06-02 20:44:52 -07:00
Andrew Waterman
84c4ae775f Improve QoR for FP->Int conversions 2017-06-02 20:44:52 -07:00
Andrew Waterman
07968df183 Refactor FP Classify 2017-06-02 20:44:52 -07:00
Andrew Waterman
6ecd58a977 Incorporate new div/sqrt unit 2017-06-02 20:44:15 -07:00
Wesley W. Terpstra
b1917e7915 coreplex: add an ISPPort trait to add cross-connect points 2017-06-02 20:43:23 -07:00
Wesley W. Terpstra
81d372137a coreplex: unconditionally insert a Splitter between tiles and l1tol2 2017-06-02 20:43:21 -07:00
Wesley W. Terpstra
d002cec6ac NodeNumberer: add an adapter to map inter-chip fabrics 2017-06-02 20:42:17 -07:00
Wesley W. Terpstra
5a2a6b0386 diplomacy: add a CustomNode type that allows direct overload of methods 2017-06-02 20:42:17 -07:00
Wesley W. Terpstra
fed1f53afa tilelink2: add a TLSplitter to be used for the ISP port 2017-06-02 20:42:17 -07:00
Wesley W. Terpstra
a4bf678954 tilelink2: fix latent Xbar truncation bug 
This was introduced when we switched to HeterogeneousBag for diplomatic IO.
It seems a lucky coincidence that nothing has run into this yet!
 2017-06-02 20:42:16 -07:00
Wesley W. Terpstra
ce12a64f4b tilelink2: support SplitterNodes 2017-06-02 20:42:16 -07:00
Wesley W. Terpstra
de39af7f65 tilelink2: make some Xbar methods reusable 2017-06-02 20:42:16 -07:00
Wesley W. Terpstra
0a2a93c27d diplomacy: add the new Splitter node type 2017-06-02 20:42:16 -07:00
Wesley W. Terpstra
c695237050 diplomacy: make :=* and :*= resolution more flexible 2017-06-02 20:42:16 -07:00
edwardcwang
cdbf67be68 Add a note to wire up jtag_mfr_id (#778) 
Close #774
 2017-06-02 18:53:14 -07:00
Wesley W. Terpstra
e0741a2097 axi4: don't map unused masters into TL source ID space 2017-06-02 16:30:16 -07:00
Wesley W. Terpstra
80c63c0da6 rocket: include hartid in cache master names 2017-06-02 15:52:23 -07:00
Wesley W. Terpstra
d25ad10592 diplomacy: require masters to have a name 2017-06-02 15:52:20 -07:00
Wesley W. Terpstra
475ac93cdf coreplex: print memory map using DTS, also write a JSON for it 2017-06-02 14:27:40 -07:00
Wesley W. Terpstra
ae8734da05 diplomacy: report cacheability in ResourceAddress 2017-06-02 14:27:40 -07:00
Wesley W. Terpstra
985d9750e6 tilelink2: Xbar QoR improvement 2017-06-02 14:27:40 -07:00
Wesley W. Terpstra
9317a00896 tilelink2: ToAXI4, sort and print AXI IDs used 2017-06-02 14:27:37 -07:00
Wesley W. Terpstra
eb14329c63 tilelink2: only combine managers of the same resources 2017-06-01 15:34:43 -07:00
Wesley W. Terpstra
1f531b1593 tilelink2: improve round robin arbiter QoR 2017-06-01 15:34:40 -07:00
Wesley W. Terpstra
5994714970 diplomacy: move manager unification to meta-data only 
Now that PMA circuits already perform address unification, there is
no QoR gained by throwing away the true and complete diplomatic
address+node information. Defer the unification to pretty printing
the DTS address map only.
 2017-06-01 15:30:20 -07:00
Wesley W. Terpstra
0fe625c52f diplomacy: improve PMA circuit QoR 2017-06-01 15:30:20 -07:00
Yunsup Lee
6124bf0cc2 sort entires in the printed address map (#773) 2017-05-31 07:45:46 -10:00
Jacob Chang
e3e77d68e6 PTW now does not require atomic memory operations, so take out the requirement (#767) 
Bug fix in CSR which manifest itself when compiling a config with no extension
 2017-05-26 13:11:15 -07:00
Andrew Waterman
dbc5e7c494 Add TLB miss performance counters (#762) 2017-05-23 12:52:25 -07:00
Andrew Waterman
b2b4c1abcd Separate tag ECC and data ECC options (#761) 2017-05-23 12:51:48 -07:00
Henry Cook
940614625e TLCacheCork: unsafe flag now _really_ unsafe (#760) 2017-05-22 19:37:11 -07:00
Wesley W. Terpstra
7f1d3c445f Plusargs -- tilelink timeout detection from the command line (#752) 
* util: PlusArg gives Chisel access to the command-line

* tilelink2: add a progress watchdog to Monitors
 2017-05-18 22:49:59 -07:00
Wesley W. Terpstra
748a48f667 unittest: balance the run times of the tests 2017-05-17 14:02:59 -07:00
Wesley W. Terpstra
bea2489507 unittest: make overall test duration configurable 2017-05-17 14:02:59 -07:00
Wesley W. Terpstra
c8ba6b2feb unittests: accept a configurable number of transactions to run 2017-05-17 14:02:59 -07:00
Wesley W. Terpstra
f6f40b1442 unit tests: all should accept timeout override 2017-05-17 14:02:59 -07:00
Wesley W. Terpstra
8c3736e0dc tilelink2: remove ready-valid fuzzer obsoleted by TLDelayer 2017-05-17 06:47:21 -07:00
Wesley W. Terpstra
1f2236cdb3 diplomacy: appease Jack by removing unused 1st bundles argument 2017-05-17 06:46:07 -07:00
Wesley W. Terpstra
f2d16d49c2 tilelink2: don't widen TLMonitor interface unnecessarily 2017-05-17 06:29:03 -07:00
Wesley W. Terpstra
191dad7800 diplomacy: provide connect access to edges without bundles 
Forcing the bundles to exist early can mess up module ownership.
 2017-05-17 06:29:03 -07:00
Megan Wachs
d8996ea85f Empty commit to force travis 2017-05-16 22:56:58 -07:00
Henry Cook
5f22e91a7f rocc: fix RoccExampleConfig 2017-05-16 16:44:53 -07:00
Henry Cook
a19fc2549e tile: add tileBus xbar 2017-05-16 16:12:01 -07:00
Wesley W. Terpstra
3e2b477c0a rational: adjust comments and add a case for N:M 2017-05-14 15:16:33 -07:00
Wesley W. Terpstra
2119df5a60 vsrc: add ClockDivider3 used to simulate unaligned clocks 2017-05-14 15:05:55 -07:00
Wesley W. Terpstra
05e7501e7a build: include chiselName and give an example of using it (#738) 2017-05-12 06:25:58 -07:00
Wesley W. Terpstra
18725a05b0 DTS tweaks (#740) 
* rocket: do not report 's' in isa string

* rocket: report the micro-architecture of the core
 2017-05-12 05:32:57 -07:00
Henry Cook
5f3a4ada1b diplomacy: add legalize method to AddressSet 2017-05-10 12:54:24 -07:00
Henry Cook
3af40bff8b tilelink: better address masking for fuzzing 2017-05-10 12:54:24 -07:00
Wesley W. Terpstra
3eaa973da7 tilelink2: add earlyAck to regression 2017-05-09 17:35:26 -07:00
Wesley W. Terpstra
3e7bdcbf5e tilelink2: Fragmenter should ignore error when not valid 2017-05-09 17:35:26 -07:00
Wesley W. Terpstra
43c9f5fe7e tilelink2: keep earlyAck Fragmenter sources distinct 2017-05-09 17:35:22 -07:00
Andrew Waterman
3a9bbd7e58 Merge branch 'master' into vectored-stvec 2017-05-08 14:08:09 -07:00
Wesley W. Terpstra
2d8a49cc06 tilelink2: Fragmenter client must request global FIFO 2017-05-08 00:56:45 -07:00
Wesley W. Terpstra
36f4584bb1 axi4: Test AXI4-Lite in regression 2017-05-08 00:31:35 -07:00
Wesley W. Terpstra
3209e58845 axi4: SRAM support 0 userBits 2017-05-08 00:31:14 -07:00
Wesley W. Terpstra
db76ff2d86 axi4: Deinterleaver must gather R also for single ID 
In order to guarantee that a complete R can be sent without
sinking B, the Deinterleaver must do its job even on AXI-Lite.
 2017-05-08 00:17:06 -07:00
Wesley W. Terpstra
8fc27b0bf2 axi4: IdIndexer; a single ID does NOT imply no response interleaving 
Some slaves may never send R until you process their B.
Thus, while there is no read response interleaving, there
is still interleaving between R and B, which breaks AXI4ToTL.
 2017-05-08 00:17:06 -07:00
Wesley W. Terpstra
4847c32599 tilelink: ToAXI4 - must interlock till last beat 
AXI4 makes no guarantee that bursts are handled atomicly.
Thus, you could be part-way through a read burst and suddenly
a write cuts ahead and is visible later, violating FIFO.
 2017-05-08 00:17:06 -07:00
Wesley W. Terpstra
8169ba6411 axi4: IdIndexer now handles 0-width IDs 2017-05-08 00:17:02 -07:00
Andrew Waterman
7eefc12705 Support vectored stvec interrupts, too 
137812654e
 2017-05-07 15:40:08 -07:00
Andrew Waterman
c6135a02df Revert "rocket: hard-wire UXL/SXL fields to 0" 
This reverts commit ea0714bfcb.

We've waffled on this matter in the priv spec: 326bec83de
 2017-05-07 15:23:21 -07:00
Andrew Waterman
dd1546fd69 Check PPN LSBs for superpage PTEs 
5a32fe8782
 2017-05-05 15:30:09 -07:00
Scott Johnson
1b3b228790 ITIM supports PutPartial 2017-05-04 00:57:52 -07:00
Andrew Waterman
398600d4da Interlock to prevent ITIM hazard when tl.a.valid & tl.d.valid & !tl.d.ready 2017-05-04 00:57:29 -07:00
Scott Johnson
1cc665717d Wes fix for AXI2TL timeout when writes backed up 2017-05-04 00:54:21 -07:00
Andrew Waterman
fa6ecdf813 Fix RVC/uncacheable instruction memory performance bug 
9c1d126965 was an incomplete fix, so
sometimes we were requesting pipeline replays when they weren't
necessary.
 2017-05-03 17:52:06 -07:00
Henry Cook
1f1240baf1 fuzzer: allow fuzzing range to be overridden 2017-05-03 15:29:14 -07:00
Megan Wachs
f8c92d2669 Merge branch 'master' into pipeline-mmio 2017-05-03 08:37:12 -07:00
Andrew Waterman
4efcb5a139 Increase frontend decoupling (#722) 
Reduce pathological RVC stalls
 2017-05-03 07:54:46 -07:00
Henry Cook
05ca88fb47 Merge branch 'master' into pipeline-mmio 2017-05-03 01:59:59 -07:00
Megan Wachs
922a8ef5e0 local_interrupts: Correct off-by-1 if there is no SEIP 2017-05-02 21:55:25 -07:00
Henry Cook
4dd3345db2 Merge branch 'master' into pipeline-mmio 2017-05-02 16:23:26 -07:00
Andrew Waterman
3a1a37d41b Support PutPartial in ScratchpadSlavePort 2017-05-02 03:07:02 -07:00
Andrew Waterman
938b089543 Remove legacy devices that use AMOALU 
I'm going to change the AMOALU API, and so I'm removing dependent dead code.
 2017-05-02 03:05:41 -07:00
Andrew Waterman
f8151ce786 Remove subword load muxing in ScratchpadSlavePort 2017-05-02 00:14:46 -07:00
Andrew Waterman
044b6ed3f9 Improve logical ops in AMOALU 
As with integer ALU, shave off some muxing.
 2017-05-02 00:14:46 -07:00
Andrew Waterman
f49172b5bc ScratchpadSlavePort doesn't support byte/halfword atomics 2017-05-02 00:14:46 -07:00
Wesley W. Terpstra
fe280187a1 axi4: Fragmenter cuts all input channel readys 
AXI4 forbids any input to lead combinationally to an output.For the AXI4ToTL
direction, front-load the cuts for {AW, AR, W}.readyAXI4ToTL makes the R and
B channels irrevocable.
 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
3d06f01a2c rocket: turn on early ack for ITIM 2017-05-01 22:53:41 -07:00