rocket-chip/scala at b1917e79154bc97c03489c91b01f61181ae39b01 - rocket-chip - Tiband Gitea

riscv/rocket-chip

History

Wesley W. Terpstra b1917e7915 coreplex: add an ISPPort trait to add cross-connect points

2017-06-02 20:43:23 -07:00

..

Configs: use a uniform syntax without Match exceptions (#507 )

2017-01-13 14:41:19 -08:00

coreplex: add an ISPPort trait to add cross-connect points

2017-06-02 20:43:23 -07:00

diplomacy: add a CustomNode type that allows direct overload of methods

2017-06-02 20:42:17 -07:00

coreplex: unconditionally insert a Splitter between tiles and l1tol2

2017-06-02 20:43:21 -07:00

jtag: make it easier to assign MFR ID externally

2017-04-14 01:03:11 -07:00

debug: Remove older version of JTAG interface as it is superseded by the one in jtag package.

2017-03-27 21:25:37 -07:00

regmapper: remove the Pipe in the RegMapper Queue

2017-04-19 21:37:37 -07:00

rocket: include hartid in cache master names

2017-06-02 15:52:23 -07:00

Add a note to wire up jtag_mfr_id (#778 )

2017-06-02 18:53:14 -07:00

Separate tag ECC and data ECC options (#761 )

2017-05-23 12:51:48 -07:00

NodeNumberer: add an adapter to map inter-chip fabrics

2017-06-02 20:42:17 -07:00

unittest: balance the run times of the tests

2017-05-17 14:02:59 -07:00

Plusargs -- tilelink timeout detection from the command line (#752 )

2017-05-18 22:49:59 -07:00