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riscv/rocket-chip
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dbc5e7c49460f99259f89fc11d979b906a307a4a
rocket-chip/src/main/scala
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Andrew WatermanandHenry Cook dbc5e7c494 Add TLB miss performance counters (#762)
2017-05-23 12:52:25 -07:00
..
config
Configs: use a uniform syntax without Match exceptions (#507)
2017-01-13 14:41:19 -08:00
coreplex
Empty commit to force travis
2017-05-16 22:56:58 -07:00
diplomacy
diplomacy: appease Jack by removing unused 1st bundles argument
2017-05-17 06:46:07 -07:00
groundtest
Fix regression in groundtest DummyPTW
2017-03-28 00:56:14 -07:00
jtag
jtag: make it easier to assign MFR ID externally
2017-04-14 01:03:11 -07:00
junctions
debug: Remove older version of JTAG interface as it is superseded by the one in jtag package.
2017-03-27 21:25:37 -07:00
regmapper
regmapper: remove the Pipe in the RegMapper Queue
2017-04-19 21:37:37 -07:00
rocket
Add TLB miss performance counters (#762)
2017-05-23 12:52:25 -07:00
rocketchip
tilelink2: remove ready-valid fuzzer obsoleted by TLDelayer
2017-05-17 06:47:21 -07:00
tile
Separate tag ECC and data ECC options (#761)
2017-05-23 12:51:48 -07:00
uncore
TLCacheCork: unsafe flag now _really_ unsafe (#760)
2017-05-22 19:37:11 -07:00
unittest
unittest: balance the run times of the tests
2017-05-17 14:02:59 -07:00
util
Plusargs -- tilelink timeout detection from the command line (#752)
2017-05-18 22:49:59 -07:00
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