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Commit Graph

5605 Commits

Author SHA1 Message Date
42e5e92d43 Update TestDriver module to support FSDB
Add support for FSDB waveform dumping using existing API.  Feature is enabled using +define+FSDB.

Change has not been fully regressed (i.e., please don't pull blindly).  Impact on existing knobs is minimal, should not affect existing functionality.  Automated Travis builds should be sufficient to assess.

Alternatively could using +define+VCS.  Chose to introduce new define because multiple simulators support FSDB dumping.
2018-01-09 09:54:34 -08:00
15c54b1c5a tile: intSinkNode belongs in HasExternalInterrupts 2018-01-08 19:38:10 -08:00
11e5b620f8 tile: disable more monitors on slave port 2018-01-08 18:42:25 -08:00
5075a93e6c util: dontTouch work-around for zero width aggregates 2018-01-08 15:58:28 -08:00
7fc8337cdb Merge pull request #1180 from freechipsproject/addrwregdesc
Allow rwReg to pass name and description to RegField for documentation.
2018-01-08 09:44:44 -08:00
a530646d15 Merge remote-tracking branch 'origin/master' into refactored_rbb 2018-01-08 09:11:27 -08:00
4fd4ae38e3 Merge pull request #1176 from freechipsproject/fix-tl-port
Fix TL MMIO port
2018-01-05 20:37:44 -08:00
3525489fff Merge pull request #1174 from freechipsproject/error-device-tracked
Claim that ErrorDevice is TRACKED
2018-01-05 17:17:22 -08:00
427b6c9ab8 Emulator: Update it to allow some hard-coded Verilog PlusArgs 2018-01-05 17:08:21 -08:00
76c5fd0c0c travis: Use newer infrastructure, but require sudo for additional disk space.
This is because as of Dec 12, 2017, Travis changed their container images and seem
to give slightly less disk space. Using a sudo image gives more disk space.
2018-01-05 17:08:21 -08:00
e6661a6982 Debug regressions: use a plusarg to enable remote bitbang. 2018-01-05 17:08:21 -08:00
b643f3dca6 debug regressions: some whitespace and null ptr cleanup 2018-01-05 17:08:21 -08:00
96dd5d8c38 Emulator example clarifications
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2018-01-05 17:08:21 -08:00
7ae6bf7611 Arguments clarification, add examples
This clarifies and provides consistent for the command line arguments
usage text.

This adds a set of examples for running the rocket-chip emulator.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2018-01-05 17:08:21 -08:00
1aa87f6578 Make emulator.cc understand HTIF arguments
This, with riscv-fesvr modifications, enables the rocket-chip emulator
to understand (and error out) if a command line argument that will
eventually be consumed by HTIF looks bad and can error out quickly.
This relies on modifications to risc-fesvr to support getopt and the
exposure of what HTIF arguments exist via the `htif.h` header.
2018-01-05 17:08:21 -08:00
3ead9a5d2d Move check on VCS inside riscv-fesvr
This removes the necessary preprocessing of riscv-fesvr arguments to
avoid situations where riscv-fesvr thinks that an argument is the
binary. Support for this is rolled into riscv-fesvr.
2018-01-05 17:08:21 -08:00
a97add954a Async Reg: Doesn't properly reset for Verilator. 2018-01-05 17:08:21 -08:00
9df3604007 emulator: No reason not to emit waveforms during reset 2018-01-05 17:08:21 -08:00
024cd52c44 debug: attempt to make the simulation deterministic by not returning until connection is made and command is receieved 2018-01-05 17:08:21 -08:00
1d3fa07c44 debug: print failures when debug tests fail, so we can see why it is failing on Travis
Cleanups, and print out log names ASAP.

Factor out gdbserver common invocation into GDBSERVER (fixing
--print-failtures).
Add --print-log-names to that command so the logfiles can be inspected
while the simulation is still running.
`RISCV=... cmd` is more idiomatic than `export RISCV=... && cmd`
2018-01-05 17:08:15 -08:00
8425086f98 Allow rwReg to pass name and description to RegField for documentation. 2018-01-05 16:59:58 -08:00
9b234216f0 debug: Install pexpect package for travis regressions 2018-01-05 16:13:19 -08:00
1549ecfb3f debug: explicitly clone riscv-tests to get to gdbserver.py 2018-01-05 16:13:11 -08:00
3de9a04272 debug regression: until XLEN fix is merged into riscv-tests, have to explicitly state the XLEN 2018-01-05 16:10:13 -08:00
bd5fe5d22e Debug regression: have to say something about memory in order to run a simple test 2018-01-05 16:10:13 -08:00
5df55d7911 debug regression: bump riscv-tools for riscv-tests fixes 2018-01-05 16:10:13 -08:00
593839e0d5 Debug: add Debug regression to Travis regressions. 2018-01-05 16:10:00 -08:00
4449dd0baa Debug regressions: Add necessary config scripts 2018-01-05 16:03:59 -08:00
e82328336e Add in a SimJTAG to connect to OpenOCD's remote-bitbang interface.
This is simpler than JTAGVPI and is supported better by Verilor.
It is also the same thing Spike uses.
2018-01-05 16:02:52 -08:00
b77b93b0b4 util: dontTouchPortsExcept 2018-01-05 14:06:00 -08:00
000cde2f8a Make ErrorDevice UNCACHEABLE instead of UNCACHED
...even though it still supports Acquire.  This avoids needing to flush
the D$ on FENCE.I because of the presence of the ErrorDevice.
2018-01-05 14:00:42 -08:00
ad0b9a0b1b Reduce cases in which FENCE.I must flush D$
Memory regions that are uncacheable or have get/put effects should not
reside in the D$, so there is no need to flush them.
2018-01-05 13:58:14 -08:00
4853d1355f rocket: dontTouch HellaCache.io.cpu.resp 2018-01-05 12:50:24 -08:00
847efde385 coreplex: dontTouch the tile_inputs wire 2018-01-05 12:47:41 -08:00
f749e986cf coreplex: fix TL MMIO port example 2018-01-05 12:29:47 +01:00
206892899f Merge pull request #1171 from freechipsproject/fix-msb-check
Enforce physical-address canonicalization
2018-01-03 12:06:18 -08:00
1bd343bcef Merge pull request #1156 from freechipsproject/has-tiles
coreplex: make HasTiles more generic
2018-01-02 19:38:17 -08:00
ee1a9485df Enforce physical-address canonicalization
When xLen > paddrBits, enforce that physical addresses are zero-extended.
This works by checking that the _virtual_ address is _sign_-extended, then
checking that its sign is positive.
2018-01-02 18:47:30 -08:00
7c9a1b0265 Correctly check for virtual-address canonicalization
The previous check was necessary but not sufficient.
2018-01-02 18:41:25 -08:00
320900f76c tile: BaseTileModule => BaseTileModuleImp 2018-01-02 17:55:54 -08:00
b0e1bc3071 tile: cake reduction
* merge HasScratchpadSlavePort into RocketTile
* merge CanHaveSharedFPUModule into BaseTileModule
2018-01-02 17:49:08 -08:00
efe7165b54 tile: BaseTile refactor, pt 2
* 2 layer cake
* no more bundle traits, only call to IO
2018-01-02 15:37:31 -08:00
1579ddb97e tile: removed RocketTileWrapper. RocketTile now HasCrossing. 2017-12-28 14:00:13 -08:00
1cd018546c tile: BaseTile refactor, pt 1
* Make dts generation reusable across tile subclasses
* First attempt to standardize tile IO nodes and connect methods
* hartid => hartId when talking about scala Ints
2017-12-26 11:04:15 -08:00
ba6dd160a3 diplomacy: allow access to sram Device info 2017-12-22 19:00:43 -08:00
7385c99435 Bump chisel3 and firrtl to get bug fixes (#1163)
Fixes #1160
2017-12-20 19:06:38 -08:00
d9c5ec4f7b coreplex: HasTiles supplies def tileParams 2017-12-20 17:18:55 -08:00
ddaeedf2d0 coreplex: make HasTiles more generic
HasTiles now deals with only extremely general tile IOs.
Some RocketTiles specific behavior moved into RocketCoreplex.
BaseTile now has optional LocalInterruptNode.
2017-12-20 17:18:55 -08:00
9b82f1098d Merge pull request #1154 from freechipsproject/bump-sbt
Bump chisel, firrtl, and sbt
2017-12-19 14:16:47 -08:00
895c4b9261 Revert "ICache: stores to the ITIM have effects (shrinking valid ITIM data) (#1144)" (#1162)
This reverts commit a542ae687e.
2017-12-19 12:16:26 -08:00