Andrew Waterman
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2d44be747a
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Fix groundtest without HTIF
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2016-06-23 12:17:26 -07:00 |
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Andrew Waterman
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30331fcaeb
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Remove HTIF; use debug module for testing in simulation
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2016-06-23 00:32:05 -07:00 |
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Andrew Waterman
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4a8e6c773a
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Fix +verbose flag for verilator
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2016-06-17 21:09:08 -07:00 |
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Donggyu Kim
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99b257316e
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replace emulator with verilator for chisel3
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2016-06-08 02:43:54 -07:00 |
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Andrew Waterman
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46bbbba5e6
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New address map
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2016-04-30 20:59:36 -07:00 |
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Andrew Waterman
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1f211b37df
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WIP on new memory map
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2016-04-27 14:57:54 -07:00 |
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Howard Mao
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6fc1e92708
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add option to print cycle count regardless of exit status
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2015-12-04 12:04:13 -08:00 |
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Howard Mao
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bbf14ddc01
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use definitions in consts header whenever possible
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2015-11-05 10:48:32 -08:00 |
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Howard Mao
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ba5a6af05c
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correctly stripe data across memory channels in simulation
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2015-11-05 10:48:32 -08:00 |
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Howard Mao
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dcef020ca0
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get multichannel simulation working in emulator
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2015-11-05 10:48:32 -08:00 |
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Yunsup Lee
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0d245741bc
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add multichannel NASTI support in Verilog testbench
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2015-11-05 10:48:32 -08:00 |
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Howard Mao
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9dabcab9c2
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Get rid of MemIO in Top and replace with AXI throughout
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2015-11-05 10:48:32 -08:00 |
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Howard Mao
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38a9b23ce7
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add a flag to only log and dump after a certain number of cycles
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2015-09-22 10:32:31 -07:00 |
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Howard Mao
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4496e8d4e2
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make sure htif_emulator properly sets memory size
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2015-09-22 10:32:31 -07:00 |
|
Iori YONEJI
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0ac6172525
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Add "-memsize" flag to emulator
- Allow user to set memory size (in MiB) used by emulator.
- if memory is exhausted, warn user about memory shortage.
Close #3
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2015-08-26 17:53:37 -07:00 |
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Henry Cook
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d3ccec1044
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Massive update containing several months of changes from the now-defunct private chip repo.
* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
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2015-07-02 14:43:30 -07:00 |
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Yunsup Lee
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1cfd9f5a0e
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add LICENSE
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2014-09-12 10:15:04 -07:00 |
|
Yunsup Lee
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275b72368b
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add CONFIG to the name of simulator executable
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2014-09-11 22:11:58 -07:00 |
|
Yunsup Lee
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c03c09ec31
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update for rocket-chip release
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2014-08-31 20:26:55 -07:00 |
|
Andrew Waterman
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7f23257873
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Print out random seed if test fails
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2014-03-17 15:35:32 -07:00 |
|
Andrew Waterman
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d055c0ebaf
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Push rocket/hardfloat/chisel
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2014-03-04 16:39:06 -08:00 |
|
Andrew Waterman
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dfc13236d1
|
Linux works again!
|
2014-01-16 12:44:29 -08:00 |
|
Andrew Waterman
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ab6cd9c9e8
|
Update chisel, rocket
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2013-12-09 15:09:48 -08:00 |
|
Andrew Waterman
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c55eee7244
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Pass target machine exit code back to host OS
|
2013-10-29 13:24:09 -07:00 |
|
Andrew Waterman
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fbdbb01232
|
update to new isa; disable vector tests
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2013-09-12 17:04:03 -07:00 |
|
Andrew Waterman
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ae0716fb6d
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Use chisel printf for logging
|
2013-06-13 10:53:23 -07:00 |
|
Andrew Waterman
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cfa86dba4f
|
add FPGA test bench
The memory models now support back pressure on the response.
|
2013-05-02 04:59:32 -07:00 |
|
Andrew Waterman
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d2e1828714
|
gracefully kill htif thread, fixing tty stuff
|
2013-05-02 04:59:32 -07:00 |
|
Andrew Waterman
|
def11e44b8
|
don't pipe stdout to vcd2vpd
|
2013-03-25 17:01:13 -07:00 |
|
Andrew Waterman
|
c6695bee7c
|
fix emulator HTIF interface bug
|
2013-02-20 16:11:21 -08:00 |
|
Andrew Waterman
|
dbb61306f0
|
randomize coreid mapping
|
2013-01-26 16:13:14 -08:00 |
|
Andrew Waterman
|
4077b22929
|
include fesvr as a library; improve harnesses
|
2013-01-24 23:57:23 -08:00 |
|
Andrew Waterman
|
d911e635d6
|
simplify c++ memory models; support +dramsim flag
works for both vlsi and emulator
|
2012-12-04 07:04:26 -08:00 |
|
Andrew Waterman
|
6d47d18c2b
|
catch sigterm to gracefully exit (fixes vcd)
|
2012-11-20 05:40:44 -08:00 |
|
Andrew Waterman
|
b58214d7e3
|
remove more global constants
|
2012-11-17 17:25:43 -08:00 |
|
Andrew Waterman
|
cf05b604b3
|
upgrade to new rocket; improve vlsi makefiles
|
2012-11-17 07:21:29 -08:00 |
|
Andrew Waterman
|
e2afae011a
|
factor out global constants
|
2012-11-06 08:18:40 -08:00 |
|
Andrew Waterman
|
4ed2d614a2
|
update to new rocket; retime fpu in dc-syn
|
2012-11-04 16:43:02 -08:00 |
|
Andrew Waterman
|
edf0eeed01
|
integrate updated rocket/uncore
|
2012-10-18 17:51:41 -07:00 |
|
Miquel Moreto
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5d75ddc553
|
Added dramsim2 memory model to the emulator backend
|
2012-10-14 14:06:28 -07:00 |
|
Huy Vo
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93a0182b96
|
everything to get emulator working
|
2012-10-01 19:30:11 -07:00 |
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