Andrew Waterman
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2d1d7266f5
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Fix RV64 badaddr value on instruction faults with large addresses
We were relying on ALU passthrough for this, but failed to override the
ALU dw argument, so bits above 31 could be discarded.
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2016-08-15 23:09:09 -07:00 |
Howard Mao
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38e0967816
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strip DMA and RoCC CSRs out of rocket and uncore (#201)
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2016-08-15 23:08:55 -07:00 |
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Howard Mao
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47a0c880a4
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make sure TLId set in Periphery
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2016-08-15 13:58:23 -07:00 |
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Howard Mao
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e939af88aa
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explicitly set TLId for bus TL ports
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2016-08-15 12:46:29 -07:00 |
|
Howard Mao
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2c39f039b5
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make external address map order overrideable
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2016-08-15 11:40:28 -07:00 |
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Howard Mao
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fb476d193c
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refactor main App for better code re-use
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2016-08-11 16:15:23 -07:00 |
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Howard Mao
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a756856d84
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make sure coreplex sources included in make dependencies
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2016-08-11 14:27:03 -07:00 |
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Howard Mao
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e0ae039235
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fix config string generation for extra devices
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2016-08-11 10:44:32 -07:00 |
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Howard Mao
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647dbefd9b
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split coreplex off into separate package
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2016-08-10 18:04:22 -07:00 |
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Howard Mao
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163cba6a85
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make sure all regressions actually run
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2016-08-10 14:52:06 -07:00 |
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Howard Mao
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4bfa7ceb6a
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unit tests in Coreplex instead of Tile
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2016-08-10 11:26:14 -07:00 |
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Howard Mao
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571d579b86
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get unit tests working again
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2016-08-10 11:23:07 -07:00 |
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Howard Mao
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0ee1ce4366
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separate Coreplex and TopLevel parameter traits
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2016-08-10 09:49:56 -07:00 |
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Howard Mao
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f95d319162
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don't use secondary external address map; collapse submap instead
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2016-08-09 22:29:38 -07:00 |
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Howard Mao
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2645f74af2
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clean up addrmap flatten function
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2016-08-09 22:14:32 -07:00 |
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Howard Mao
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33f13d5c49
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don't repeat external addr map base
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2016-08-09 21:20:54 -07:00 |
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Howard Mao
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3ea2f4a6c4
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refactor top-level into coreplex and platform
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2016-08-09 18:26:52 -07:00 |
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Howard Mao
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993da60f2c
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relax address map alignment requirement
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2016-08-09 18:25:32 -07:00 |
|
Howard Mao
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33d5905c50
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don't synthesize vsim verilog in Travis
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2016-08-09 18:24:59 -07:00 |
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Howard Mao
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405294167f
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fix TL -> Nasti converter w id
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2016-08-09 18:24:23 -07:00 |
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Andrew Waterman
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2906c75167
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Remove fsim, as it is the same as vsim, modulo CONFIG
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2016-08-09 15:42:22 -07:00 |
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Andrew Waterman
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1b8f919db2
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Remove unused CoreName parameter
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2016-08-09 15:24:59 -07:00 |
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Andrew Waterman
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458520c8f6
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Use a generic UInt for TileLink op sizes, rather than MT_xx enum
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2016-08-09 15:24:51 -07:00 |
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Andrew Waterman
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a857b08c59
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[rocket] compute D$ tag bits based upon # of arbiter ports
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2016-08-09 14:40:48 -07:00 |
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Howard Mao
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2a5aeeae24
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add sbt pack plugin (#197)
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2016-08-08 19:31:03 -07:00 |
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Howard Mao
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dd1fed41b6
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generate BootROM contents from assembly code
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2016-08-05 16:39:21 -07:00 |
Palmer Dabbelt
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dab96096b4
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Add firrtl build dependencies
Without this when I update firrtl the new version doesn't get built, so
my build is constantly failing.
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2016-08-05 14:45:00 -07:00 |
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Howard Mao
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9fa5b228b2
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allow extra devices and top-level ports to be added without changing RocketChip.scala
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2016-08-04 14:06:14 -07:00 |
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Howard Mao
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9c4e57aea5
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example Rocc accelerator fixes
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2016-08-04 11:17:13 -07:00 |
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Howard Mao
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410e3e5366
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make sure TraceGen gets correct addresses
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2016-08-04 11:08:25 -07:00 |
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Howard Mao
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0a85e92652
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Allow additional internal MMIO devices to be created without changing BaseConfig
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2016-08-04 11:04:52 -07:00 |
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Andrew Waterman
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cc0f8962fb
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[rocket] take physical memory attribute check off critical path
Cache the attributes in the TLB instead.
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2016-08-02 17:21:03 -07:00 |
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Andrew Waterman
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76f33d88a6
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[rocket] Respect physical memory protection during page table walks
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2016-08-02 17:20:49 -07:00 |
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Andrew Waterman
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5d4f6383f2
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[rocket] Automatically kill D$ access on address exceptions
Doing this internally to the cache eliminates a long control path
from the cache to the core and back to the cache.
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2016-08-02 17:20:49 -07:00 |
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Andrew Waterman
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b54db0ba23
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[rocket] don't update BTB on not-taken branches
Only update the BHT; don't set the target prediction to pc+4.
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2016-08-02 17:20:49 -07:00 |
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Andrew Waterman
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64bde1060c
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[rocket] remove unused code in ibuf
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2016-08-02 15:26:09 -07:00 |
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Andrew Waterman
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2ce702dc0a
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[rocket] fix PTW critical path
Pipeline the killing of a D$ request following a PTW cache hit.
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2016-08-02 15:19:48 -07:00 |
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Andrew Waterman
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7e9d139e49
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[rocket] remove rocket-specific require() from HasCoreParameters
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2016-08-02 15:19:48 -07:00 |
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Andrew Waterman
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791a27748b
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Update firrtl and remove firrtl hack in plic
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2016-08-02 15:19:48 -07:00 |
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Howard Mao
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f04aefc95c
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get rid of deprecated ZynqAdapter
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2016-08-02 13:14:20 -07:00 |
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Howard Mao
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63b814fcd7
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only run the important (high coverage) tests in regression suite
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2016-08-02 10:54:05 -07:00 |
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Howard Mao
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b7723f1ff8
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make unit tests local to the packages being tested
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2016-08-01 17:02:00 -07:00 |
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Howard Mao
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98eede0505
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some refactoring in RocketChip top-level
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2016-08-01 17:02:00 -07:00 |
Megan Wachs
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55c992bb3a
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Use FoldRight() instead of for loop
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2016-08-01 16:56:33 -07:00 |
|
Megan Wachs
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8db2e8829f
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Allow aggregate CONFIG on Command Line
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2016-08-01 14:24:16 -07:00 |
|
Andrew Waterman
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fe670e5421
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Stop using deprecated FileSystemUtilities to create files
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2016-07-31 18:04:56 -07:00 |
|
Andrew Waterman
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832e56d3c7
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Fix toBits/toUInt/toSInt deprecation warnings
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2016-07-31 17:13:52 -07:00 |
|
Andrew Waterman
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a6e009d8de
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[rocket] Fix frontend mask when fetchWidth == 1
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2016-07-31 15:21:17 -07:00 |
|
Andrew Waterman
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c49dad2e9d
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Improve PTW QoR
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2016-07-29 17:56:42 -07:00 |
|
Andrew Waterman
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cc635c386f
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Make Chisel3 the default version for SBT
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2016-07-29 17:56:42 -07:00 |