riscv/rocket-chip
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1e7480b6fc
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159 Commits

Author SHA1 Message Date
Wesley W. Terpstra
1e7480b6fc tilelink2 Monitor: work around for firrtl/verilator performance issue 
Big Vec()s cause problems for these tools.
 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
ec2030df31 tilelink2 Legacy: convert TL1 atomic operand size 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
e5da3eb8bb tilelink2 Atomics: support arithmetic atomics 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
5b80fe5b51 tilelink2 Atomics: support Logical AMOs 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
4066fbe18f tilelink2 RAMModel: exploit latency to remove bypass 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
e0ade8c5a9 tilelink2 Atomics: exploit minLatency to eliminate bypass 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
3bb2580223 tilelink2 Monitor: detect minLatency violations 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
2b24c4b1b4 tilelink2: most adapters can wipe away latency 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
c115913624 tilelink2 Buffer: increase the minLatency on ports 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
05beb20dc4 tilelink2: specify the minLatency for SRAM+RR 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
44277c1db3 tilelink2 Parameters: include a minLatency parameter for optimization 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
cf39c32b0e tilelink2 Fuzzer: test Atomics 2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
2b9403633d tilelink2 RAMModel: support (by ignoring) atomics 2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
ce204f604a tilelink2 AtomicAutomata: prototype flow control complete 2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
42b10356fa tilelink2: add a general-purpose Arbiter 2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
7636e772c8 tilelink2 Fuzzer: only generate legal atomics 2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
f5d604d8f8 tilelink2 Parameters: poison ports with unsafe atomics 
We need to detect if an AtomicAutomata's output ever gets mixed
with some other source of operations.
 2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
d1151e2f0f tilelink2 Nodes: split connect into eager and lazy halves 2016-09-22 15:18:50 -07:00
Wesley W. Terpstra
684072023f tilelink2 Monitor: make it a LazyModule in the hierarchy 2016-09-22 15:14:20 -07:00
Wesley W. Terpstra
def497861b tilelink2 Bundles: add 1-way snoop bundles 2016-09-22 15:14:20 -07:00
Wesley W. Terpstra
69a1f8cd1f tilelink2 Monitor: detect if sources are mishandled 2016-09-22 15:14:19 -07:00
Albert Ou
d76b762657 tilelink2 Fragmenter: Mask low bits of D channel addr_lo 
This fixes an issue where passing addr_lo through unchanged triggered
unaligned address assertions in the Monitor.
 2016-09-22 12:36:28 -07:00
Howard Mao
cd96a66ba6 replace verilog clock divider with one written in Chisel 2016-09-22 11:32:29 -07:00
Yunsup Lee
7afd630d3e add multiclock support to Coreplex 2016-09-21 16:55:26 -07:00
Henry Cook
335e866176 [unittest] Parallelize UnitTestSuite (#319) 
* [unittest] Parallelize UnitTestSuite so all tests have their own timer, runs until all finish or any timeout. Adds SimpleTimer.

* [util] Timer spacing cleanup

* [unittest] Remove Config reference to UnitTestTimeout
 2016-09-21 13:05:22 -07:00
Andrew Waterman
12d0c00822 Fix mtime RegField handling 
RegField.bytes was unconditionally overwriting mtime, preventing it
from ever ticking.  Avoid RegField.bytes by splitting mtime into
a Seq of words.
 2016-09-20 15:00:52 -07:00
Wesley W. Terpstra
9817a00ed9 tilelink2: Fuzzer should check address validity before injection 2016-09-17 17:07:21 -07:00
Wesley W. Terpstra
b11839f5a1 tilelink2: differentiate fast/safe address lookup cases 2016-09-17 17:04:18 -07:00
Wesley W. Terpstra
b4baae4214 tilelink2: minimize Xbar decode logic 2016-09-17 16:14:25 -07:00
Wesley W. Terpstra
76d8ed6a69 tilelink2: remove 'strided'; !contiguous is clearer 2016-09-17 16:14:25 -07:00
Wesley W. Terpstra
fa0f119f3c tilelink2: consider the implications of negative address mask 2016-09-17 16:14:22 -07:00
Wesley W. Terpstra
e437508548 tilelink2: track interrupt connectivity like in TL2 2016-09-17 14:43:48 -07:00
Wesley W. Terpstra
6c3269a1d8 SRAM: optionally (default: true) executable 2016-09-17 00:19:37 -07:00
Wesley W. Terpstra
e749558190 ROM: optionally (default: true) executable 2016-09-17 00:19:09 -07:00
Wesley W. Terpstra
8876d83640 Prci: preserve Andrew's preferred clint name 2016-09-16 17:28:47 -07:00
Wesley W. Terpstra
a357c1d42e tilelink2: create DTS for devices automagically 2016-09-16 17:28:47 -07:00
Wesley W. Terpstra
2587234838 tilelink2 TLNodes: capture nodePath in {Client,Manager}Parameters 2016-09-16 17:28:47 -07:00
Wesley W. Terpstra
915a929af1 tilelink2: Nodes can now mix context into parameters 2016-09-16 17:28:47 -07:00
Wesley W. Terpstra
dae0918c85 tilelink2 RegisterRouter: support undefZero 2016-09-16 16:09:00 -07:00
Wesley W. Terpstra
f0f553f227 tilelink2 RegisterRouterTest: work around firrtl warning 
Using io.wready leads to verilog that reads from the output...

Lint-[PCTIO-L] Ports coerced to inout
/scratch/terpstra/federation/rocket-chip/vsim/generated-src/UnitTestHarness.UnitTestConfig.v, 24860
"io_wready"
  Port "io_wready" declared as output in module "RRTestCombinational_29" may
  need to be inout. Coercing to inout.
 2016-09-16 16:09:00 -07:00
Wesley W. Terpstra
3fcc1a4460 tilelink2 RegisterRouterTest: don't couple fire into helpers 2016-09-16 16:09:00 -07:00
Wesley W. Terpstra
2210e71f42 tilelink2 AddressDecoder: validate output of optimization 2016-09-16 16:09:00 -07:00
Wesley W. Terpstra
023a54f122 tilelink2 AddressDecoder: improved heuristic 2016-09-16 16:09:00 -07:00
Andrew Waterman
86b70c8c59 Rename PRCI to CoreplexLocalInterrupter 
That's all it's doing (there wasn't much PRC).
 2016-09-16 14:26:34 -07:00
Wesley W. Terpstra
4b1de82c1d RegField: separate UInt=>bytes and bytes=>regs 2016-09-16 14:24:28 -07:00
Wesley W. Terpstra
943c36954d tilelink2 RegField: .bytes should update more than one byte! 2016-09-16 14:24:24 -07:00
Andrew Waterman
6134384da4 Fix deprecation warnings 2016-09-16 14:24:19 -07:00
mwachs5
a031686763 util: Do BlackBox Async Set/Reset Registers more properly (#305) 
* util: Do Set/Reset Async Registers more properly

The way BlackBox "init" registers were coded before was
not really kosher verilog for most synthesis tools.
Also, the enable logic wasn't really pushed down into the flop.

This change is more explicit about set/reset flops,
again this is only a 'temporary' problem that would go away
with parameterizable blackboxes (or general async reset support).

* Tabs, not spaces, in Makefiles

* util: Fix typos in Async BB Reg Comments
 2016-09-16 13:50:09 -07:00
Andrew Waterman
a94b4af92d Simplify AsyncResetRegVec and make AsyncResetReg companion object 2016-09-16 11:25:10 -07:00
Wesley W. Terpstra
dd19e0911e tilelink2: handle bus width=1 2016-09-15 22:15:11 -07:00