Wesley W. Terpstra 1e7480b6fc tilelink2 Monitor: work around for firrtl/verilator performance issue ... Big Vec()s cause problems for these tools.		2016-09-22 15:18:54 -07:00
..
agents	move junctions utils into top-level utils package	2016-09-13 20:47:04 -07:00
coherence	reorganize moving non-submodule packages into src/main/scala	2016-08-19 13:45:23 -07:00
converters	use named constants to set AXI resp, cache, and prot fields	2016-09-14 21:16:54 -07:00
devices	tilelink2: specify the minLatency for SRAM+RR	2016-09-22 15:18:54 -07:00
tilelink	add multiclock support to Coreplex	2016-09-21 16:55:26 -07:00
tilelink2	tilelink2 Monitor: work around for firrtl/verilator performance issue	2016-09-22 15:18:54 -07:00
util	util: Do BlackBox Async Set/Reset Registers more properly (#305)	2016-09-16 13:50:09 -07:00
Builder.scala	Use CDEMatchError for improved performance (#304)	2016-09-15 19:47:18 -07:00
Consts.scala	reorganize moving non-submodule packages into src/main/scala	2016-08-19 13:45:23 -07:00
Package.scala	reorganize moving non-submodule packages into src/main/scala	2016-08-19 13:45:23 -07:00