Wesley W. Terpstra
1a87ed1193
coreplex: add externalSlaveBuffers configuration option
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
fd8a51a910
coreplex: rename externalBuffers to externalMasterBuffers
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
4911a7d44f
tilelink Bus: toAsyncSlaves now supports BufferChains
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
040f7e1d49
tilelink: add Bus.toSyncSlaves for easy BufferChain attachment
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
d5c6494f59
tilelink: Bus.toRationalSlaves can have a BufferChain
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
80965e8230
tilelink Buffer: use new :=? adapter API
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
1b705f62f6
diplomacy: support :=? for unknown star inference
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
6bfea86dbf
config: support p.lift(key) to optionally return a value
2017-09-07 16:03:34 -07:00
Wesley W. Terpstra
2d93262f71
RationalCrossing: use ShiftQueues
...
These are faster and small don't cost much more.
2017-09-07 16:03:34 -07:00
Wesley W. Terpstra
50d5d8c1fd
ShiftQueue: added a helper object
2017-09-07 16:03:34 -07:00
Wesley W. Terpstra
3e3024c256
ShiftQueue: fix bug in !flow case
2017-09-07 16:03:34 -07:00
Wesley W. Terpstra
ed70b243bd
plic: support a configurable number of interrupt register stages
2017-09-07 16:03:34 -07:00
Wesley W. Terpstra
9b55063de6
clint: support a configurable number of interrupt register stages
2017-09-07 16:03:34 -07:00
Megan Wachs
126d56b254
synchronizers: I learn how foldRight works
2017-09-07 10:48:27 -07:00
Megan Wachs
1da6cb85ab
shiftReg: Make it so that register '0' is always closest to the q output, regardless of the type of shift register created.
2017-09-07 09:57:50 -07:00
Megan Wachs
dcafb5fea3
Merge remote-tracking branch 'origin/master' into async_reg
2017-09-06 11:07:19 -07:00
Megan Wachs
3c4b472f66
shift regs: remove some unnecessary primitives, and add some that actually are necessary
2017-09-06 10:37:59 -07:00
Jim Lawson
f1b7666d21
Jtagresettobool - add explicit toBool cast now required on reset. ( #984 )
...
Add explicit toBool cast on reset, for chisel3 compatability
2017-09-06 09:49:47 -07:00
Megan Wachs
777f052f95
regs: Add named/initial value ShiftRegister primitives so they are all in one place
2017-09-05 17:32:53 -07:00
Wesley W. Terpstra
b1cacc56ad
SystemBus: restore correct order of FIFOFixer and Buffer
2017-09-05 16:41:39 -07:00
Wesley W. Terpstra
b74a419bfb
FrontBus: FIFOFixer should not have a buffer between it and Xbar
2017-09-05 16:27:57 -07:00
Megan Wachs
e9e46db600
sync reg: Rename the file to reflect the more generic shift registers also in the file.
2017-09-05 15:54:25 -07:00
Megan Wachs
5df23c5514
Synchronizers: remove some newlines and unncessary gen's
2017-09-05 15:17:21 -07:00
Wesley W. Terpstra
e65f49b89a
FrontBus: attach to splitter for cross-chip visibility
2017-09-05 15:03:41 -07:00
Wesley W. Terpstra
5886025b1a
sbus => pbus: 2 buffers should already be enough
...
There is a buffer on the sbus backside.
There is a buffer on the pbus frontside.
Between them is only an AtomicAutomata.
That should be enough for most designs.
2017-09-05 15:03:38 -07:00
Henry Cook
a902e15987
pbus: clarify that we are adding buffers when attaching to sbus
2017-09-05 15:03:38 -07:00
Henry Cook
8fc4d78c84
frontbus: provide fifofixer on the side of the front bus where masters connect
2017-09-05 15:03:38 -07:00
Megan Wachs
667d966410
TLBuffer: Create a wrapper module for TLBufferChain, to allow for more stable naming
2017-09-05 15:03:38 -07:00
Megan Wachs
94f06dc85c
pbus: turn down overkill buffering between PBus and SBus
2017-09-05 15:03:38 -07:00
Megan Wachs
c353f68dc0
buses: name dummy buffers too
2017-09-05 15:03:38 -07:00
Henry Cook
3bde9506c6
coreplex: allow buffer chains on certain bus ports
2017-09-05 15:03:36 -07:00
Megan Wachs
57d0360c35
frontbus: Name the connection.
2017-08-30 18:07:34 -07:00
Megan Wachs
c99afe4c66
buses: Name all the things.
2017-08-30 17:31:42 -07:00
Henry Cook
32cb358c81
coreplex: include optional tile name for downstream name stabilization
2017-08-30 15:48:55 -07:00
Megan Wachs
183fefb2b9
Front/SystemBus: allow naming the intermediate TLNodes that get sprinkled in
2017-08-30 15:27:56 -07:00
Wesley W. Terpstra
d5b62dffda
SystemBus: add stupidly many (4 more) buffers from sbus=>pbus
...
This should probably be reverted.
2017-08-30 14:22:49 -07:00
Henry Styles
f7330028cc
Add optional frontbus for peripherals mastering into SBus. Switch FF and Buffer order on non-tile masters into SBus. Buffer non-L2 side of splitter
2017-08-30 14:22:49 -07:00
Wesley W. Terpstra
173f185b17
Merge pull request #976 from freechipsproject/system-buffer
...
SystemBus: add output buffering
2017-08-30 23:22:13 +02:00
Wesley W. Terpstra
656609d610
SystemBus: split FIFOFixers along bus boundaries
...
If you have a system with a lot of periphery slaves, you wan to FIFO fix
them on the periphery bus rather than paying the circuit cost at the sbus.
2017-08-30 13:28:11 -07:00
Megan Wachs
a3bc5f2e33
synchronizers: Add a generic shift register and then extend from it, since an asynchronously resettable shift register is also a useful primitive
2017-08-30 12:59:16 -07:00
Megan Wachs
8139014c9e
syncrhonizers: Remove unused sync from superclass
2017-08-30 12:33:03 -07:00
Megan Wachs
9dd6c4c32d
synchronizers: New chisel ways of cloning type and use simpler lambda function
2017-08-30 12:11:14 -07:00
Megan Wachs
bd32f0c122
synchronizers: properly pass parameters up to the superclass
2017-08-30 11:58:25 -07:00
Megan Wachs
483e63da19
synchronizers: Correctly pass the width through
2017-08-30 11:50:25 -07:00
Megan Wachs
a62ce0afe6
TLBuffer: Add a nodedebugstring for quick browsing of the properties of the buffer.
2017-08-29 10:36:46 -07:00
Megan Wachs
c473538e36
Merge remote-tracking branch 'origin/master' into async_reg
2017-08-28 17:19:03 -07:00
Megan Wachs
451334ac73
Add 1-deep synchronizer register for output of AsyncQueue
2017-08-28 17:18:54 -07:00
Wesley W. Terpstra
bf19440db5
SystemBus: use a full buffer on slaves
2017-08-26 02:47:04 -07:00
Megan Wachs
85c39b2f97
syncregs: Not sure the use case for SynchronizerShiftRegInit, so remove it YAGNI
2017-08-24 17:47:04 -07:00
Megan Wachs
4e773f4738
syncregs: Use synchronizer primivites for LevelSyncCrossing
2017-08-24 17:42:31 -07:00
