Wesley W. Terpstra
b7963eca4e
copyright: ran scripts/modify-copyright
2016-11-27 22:15:43 -08:00
Wesley W. Terpstra
e2ec1d00ad
copyright: normalize /// to // in comments
2016-11-27 22:15:43 -08:00
Wesley W. Terpstra
a0e10aec05
uncore: removed obsolete Builder file
2016-11-27 22:15:43 -08:00
Wesley W. Terpstra
4146f6a792
TLB: do not access illegal addresses ( #460 )
2016-11-26 15:11:42 -08:00
Wesley W. Terpstra
a17753983a
coreplex: allow legacy devices to override the config string ( #458 )
2016-11-25 19:38:24 -08:00
Wesley W. Terpstra
233280e7d2
AsyncBundle: save a wasted bit when depth=1
2016-11-25 18:11:01 -08:00
Wesley W. Terpstra
d755edffcc
DebugTransport: use ToAsyncDebugBus for correct depth
2016-11-25 18:10:28 -08:00
Wesley W. Terpstra
2b80386a9e
rocketchip: TileInterrupts needs a TLCacheEdge ( #456 )
2016-11-25 17:02:29 -08:00
Wesley W. Terpstra
1e0aca7358
dcache: the high bit of s2_req.typ is the SIGN bit (not size) ( #455 )
2016-11-25 15:26:22 -08:00
Wesley W. Terpstra
0baa1c9a45
coreplex: CacheBlockOffsetBits was wrong!
...
This bug is ancient. I don't understand how it never mattered before.
Anyway, in processors with a custom CacheBlockBytes, this value is wrong!
The symptom is that TL1 components end up missing high address bits.
This causes, for example, a system to jump to 0 instead of RAM.
I don't understand how this very serious bug did not cause problems before.
2016-11-24 18:32:44 -08:00
Wesley W. Terpstra
a670f63c81
periphery: a handy trait to turn-off ExtMem
2016-11-23 20:44:45 -08:00
Wesley W. Terpstra
30e890b480
diplomacy: include InternalNodes for AXI4 and TL
2016-11-23 20:44:45 -08:00
Wesley W. Terpstra
9f1c668c4f
config: when modifying Parameters, subordinate lookups use top
2016-11-23 20:44:45 -08:00
Wesley W. Terpstra
566cc9e60b
rocketchip: RTCPeriod config
2016-11-23 20:44:45 -08:00
Wesley W. Terpstra
e87f54d4f7
rocketchip: traits for adding external TL2 ports
2016-11-23 20:44:42 -08:00
Wesley W. Terpstra
4b9dc78951
rocketchip: add a parameter-controlled debug port
2016-11-23 15:35:53 -08:00
Henry Cook
38c5af5bad
[rocket] cleanup mshr logic
2016-11-23 12:09:56 -08:00
Henry Cook
dae6772624
factor out common cache subcomponents into uncore.util
2016-11-23 12:09:35 -08:00
Henry Cook
c65c255815
[coreplex] TileId moved to groundtest
2016-11-23 12:08:45 -08:00
Wesley W. Terpstra
1d3cad3671
tilelink2 SourceShrinker: handle degenerate cases for free
2016-11-22 22:17:30 -08:00
Wesley W. Terpstra
1e7d597fd3
rocketchip: don't waste too many sources on the AXI master port
2016-11-22 21:48:41 -08:00
Wesley W. Terpstra
c0b27999ea
tilelink2 SourceShrinker: a concurrency reducing adapter
2016-11-22 21:43:38 -08:00
Wesley W. Terpstra
0097274ea3
Broadcast: single-cycle response is possible
2016-11-22 20:45:40 -08:00
Wesley W. Terpstra
437be0f36a
PositionalMultiQueue: use a UInt instead of Reg(Vec(Bool))
...
This results in much less Verilog to simulate
2016-11-22 20:39:38 -08:00
Wesley W. Terpstra
f9de7173cc
PositionalMultiQueue: use 1-write n-read Mem instead of Reg(Vec(...))
2016-11-22 18:46:11 -08:00
Wesley W. Terpstra
d9a203b0f0
PositionalMultiQueue: convert 'next' to a single write port
2016-11-22 18:38:55 -08:00
Wesley W. Terpstra
13190a5de0
rocketchip: re-add AXI4 interface
2016-11-22 17:27:58 -08:00
Wesley W. Terpstra
c230580157
coreplex: rename RocketPlex => RocketTiles
2016-11-22 17:27:58 -08:00
Wesley W. Terpstra
bbabcf67ff
coreplex: width adapter should happen as part of coherence manager
...
In the future we will want the L2 to be wider on the backside so that
we can take advantage of fat DDR controllers (256bits/beat).
2016-11-22 17:27:58 -08:00
Wesley W. Terpstra
a140b07009
rocketchip: cut coreplex from rocketchip
2016-11-22 17:27:58 -08:00
Wesley W. Terpstra
c80ee06472
rocketchip: configString is a lazy property of outer
2016-11-22 17:27:58 -08:00
Andrew Waterman
5f3fb64ef0
Per ABI, only x1 and x5 should be treated as function returns
...
We were doing so for x3 and x7, as well, which could reduce performance
for compilers that happen to perform indirect jumps via t2 (x7).
2016-11-22 12:01:05 -08:00
Wesley W. Terpstra
3d644b943c
coreplex: configString is a property of the RISCVPlatform
2016-11-21 21:13:26 -08:00
Wesley W. Terpstra
e8be365b5d
rocketchip: remove GlobalAddrMap completely
2016-11-21 21:13:26 -08:00
Wesley W. Terpstra
5fe107bb07
rocket: pass scratchpad address to block dcache
2016-11-21 21:13:26 -08:00
Wesley W. Terpstra
c18bc07bbc
TLB: determine RWX from TL2 properties directly
2016-11-21 21:13:26 -08:00
Henry Cook
28c6be90ab
[rocket] require refillcycesperbeat == 1 and remove flowthroughserializer
2016-11-20 19:36:51 -08:00
Henry Cook
ff9b5bf8fc
[rocket] nbdcache release bugfix
2016-11-20 19:07:06 -08:00
Henry Cook
3f47d5b5eb
[rocket] re-enable working NBDcache (passes Tracegen)
2016-11-19 19:19:16 -08:00
Henry Cook
c31b41a7ac
[tl2] add grant finisher comment
2016-11-19 19:16:43 -08:00
Colin Schmidt
9dd12545d0
[Rocket] Send correct type for iomshr reqs
...
Also contain grow param bugfix
2016-11-19 19:04:06 -08:00
Wesley W. Terpstra
32a1c27441
rocket: disable nbdcache until it's fully ported
2016-11-18 19:55:24 -08:00
Wesley W. Terpstra
452bb2fc80
dcache fix TinyConfig
2016-11-18 19:50:34 -08:00
Wesley W. Terpstra
d1328a6b6f
rocketchip: remove most uses of GlobalAddrMap
2016-11-18 19:38:02 -08:00
Henry Cook
2976fd84e4
[rocket] resolve cde/config conflicts
2016-11-18 19:11:34 -08:00
Henry Cook
8b908465e0
[tl2] convert NBDcache to TL2 (WIP; compiles but untested)
2016-11-18 19:04:06 -08:00
Henry Cook
5f1cc19d71
[tl2] fix comment explaining permissions
2016-11-18 19:02:17 -08:00
Henry Cook
10112da4e7
[tl2] won't need putthrough opcode
2016-11-18 19:02:17 -08:00
Wesley W. Terpstra
001d9821bd
Merge remote-tracking branch 'origin/master' into tl2-tile
2016-11-18 18:19:41 -08:00
Wesley W. Terpstra
5b594ced29
Plic: support 0 interrupts gracefully
2016-11-18 18:07:44 -08:00