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riscv
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rocket-chip
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f9de7173cc
rocket-chip
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src
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main
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scala
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Wesley W. Terpstra
f9de7173cc
PositionalMultiQueue: use 1-write n-read Mem instead of Reg(Vec(...))
2016-11-22 18:46:11 -08:00
..
coreplex
rocketchip: re-add AXI4 interface
2016-11-22 17:27:58 -08:00
diplomacy
tilelink2 Xbar: merge the AddressSets of fractured managers
2016-11-03 22:18:28 -07:00
groundtest
rocketchip: re-add AXI4 interface
2016-11-22 17:27:58 -08:00
junctions
rocketchip: remove GlobalAddrMap completely
2016-11-21 21:13:26 -08:00
regmapper
regmapper RegisterCrossing: safe AsyncQueues are overkill here
2016-10-14 18:28:31 -07:00
rocket
Per ABI, only x1 and x5 should be treated as function returns
2016-11-22 12:01:05 -08:00
rocketchip
rocketchip: re-add AXI4 interface
2016-11-22 17:27:58 -08:00
uncore
rocketchip: configString is a lazy property of outer
2016-11-22 17:27:58 -08:00
unittest
junctions: get unit tests running again
2016-11-18 17:38:46 -08:00
util
PositionalMultiQueue: use 1-write n-read Mem instead of Reg(Vec(...))
2016-11-22 18:46:11 -08:00