Henry Cook
0fdaa28694
Merge pull request #811 from freechipsproject/isp-tweaks
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Assorted changes based on ISP use cases
2017-06-20 19:24:28 -07:00
Henry Cook
bf431c0a53
groundtest: fix test ram width
2017-06-20 18:11:22 -07:00
Wesley W. Terpstra
2f2fe0a973
clint: don't ask for what you know (nTiles)
2017-06-20 17:21:53 -07:00
Henry Cook
1c97a2a94c
allow re-positionable PLIC and Clint, and change coreplex internal network names
2017-06-20 17:18:45 -07:00
Henry Cook
5552f23294
tims: explictly name them for generated address map
2017-06-20 17:18:29 -07:00
Henry Cook
6b79842e66
dcache: just left shift by untagbits to get tag
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Always safe because of the requirement on coreplex/RocketTiles.scala:126
2017-06-20 16:35:28 -07:00
Henry Cook
7521050a48
Merge pull request #810 from freechipsproject/isp-fixes
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ISP fixes
2017-06-20 16:35:06 -07:00
Wesley W. Terpstra
bb309e573f
TLSplitter: special-case the case of no split necessary
2017-06-20 14:10:25 -07:00
Wesley W. Terpstra
53f030c037
TLSplitter: default policy is roundRobin
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Track commit 274d908d98
2017-06-20 14:03:01 -07:00
Wesley W. Terpstra
1aa4f5ce33
TLSplitter: QoR improvements
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Track commit 985d9750e6
2017-06-20 14:01:07 -07:00
Wesley W. Terpstra
f6e0dd12c8
TLSplitter: ManagerUnification is not used in Xbars
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Track the change made in 5994714970
2017-06-20 13:58:30 -07:00
Andrew Waterman
f396b4142d
Merge pull request #806 from freechipsproject/mulh
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Improve integer mul/div
2017-06-20 13:01:16 -07:00
Colin Schmidt
675f183dd2
refactor ICache to be reusable by other frontends ( #808 )
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* refactor ICache to be reusable by other frontends
specifically one that would like to change the fetch width and number of
bytes in an instruction
2017-06-20 08:21:01 -07:00
Andrew Waterman
a6d9884cc0
Improve integer mul/div
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- Signed integer multiplication latency is now deterministic (before,
it would take an extra cycle if the multiplier was negative).
- High-part multiplication is now one cycle faster.
- RV64 MULW now takes half as many cycles as MUL.
- Positive remainders are now one cycle faster.
2017-06-19 12:09:21 -07:00
Shreesha Srinath
ff1f0170dc
changing SystemVerilog params to Verilog style ( #801 )
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vivado-2016.1 synthesis doesn't support SystemVerilog string type parameters
2017-06-16 22:47:12 -07:00
Richard Xia
31415060fe
Merge pull request #802 from freechipsproject/fix-decode-of-instruction-after-ebreak
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Check for rvc before declaring illegal instruction after an ebreak.
2017-06-16 15:07:24 -07:00
Richard Xia
61c39da475
Check for rvc before declaring illegal instruction after an ebreak.
2017-06-16 10:49:36 -07:00
Megan Wachs
d0f8cdd00c
Merge pull request #804 from freechipsproject/travis_cache_stages
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travis: attempt to make 2 build stages for cache
2017-06-16 07:31:56 -07:00
Wesley W. Terpstra
a89c0551b7
travis: use travis_wait again
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Timeouts due to inactivity again :-/
2017-06-15 23:04:17 -07:00
Megan Wachs
30a3e3ef55
travis: attempt to make 2 build stages for cache
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First stage builds riscv-tools, next stage builds verilator
2017-06-15 21:31:15 -07:00
Wesley W. Terpstra
93d423d202
diplomacy: optimize IdRange.contains ( #798 )
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This should make an optimal circuit for a wider class of ranges.
2017-06-15 15:56:14 -07:00
Megan Wachs
d316aeb275
Merge pull request #799 from freechipsproject/bump-riscv-tools-start-multiple-harts
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Bump riscv-tools to pick up FESVR which allows starting all harts
2017-06-15 13:55:46 -07:00
Henry Cook
5368ea60fe
Merge pull request #757 from freechipsproject/isp-port
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Inter-System-Port
2017-06-15 13:07:19 -07:00
Megan Wachs
9a789fc0cf
Bump riscv-tools to pick up FESVR which allows starting all harts
2017-06-15 11:05:07 -07:00
Jack Koenig
2665a3eb2f
Bump firrtl ( #797 )
2017-06-15 10:06:24 -07:00
Wesley W. Terpstra
c259e39fa3
Merge pull request #796 from freechipsproject/buffer-instance
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diplomacy: BufferParams can now directly create a Queue
2017-06-14 15:58:29 -07:00
Wesley W. Terpstra
1f8c4ba4ca
CoreplexNetwork: don't force a buffer on the coherence manager
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Let the l2Config.coherenceManager create its own appropriate buffers.
This can matter if you need to make sure the buffer is in the right
place in the hierarchy for hierarchical place and route.
2017-06-14 14:27:23 -07:00
Wesley W. Terpstra
4a15d47061
diplomacy: BufferParams can now directly create a Queue
2017-06-14 13:47:37 -07:00
Wesley W. Terpstra
36562ce48e
Merge pull request #794 from freechipsproject/xbar-debug
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Deal with lots of sources more gracefully.
2017-06-13 19:44:28 -07:00
Wesley W. Terpstra
c85486e67c
travis: don't give up if gcc is slow to build riscv-tools
2017-06-13 16:59:31 -07:00
Wesley W. Terpstra
b4b165112c
PeripheryErrorSlave: do not put a TLMonitor between the fragmenter and slave
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This edge has the largest number of source bits by far. Let's just exclude it.
2017-06-13 16:59:29 -07:00
Wesley W. Terpstra
94f85e8bc8
tilelink2: TLMonitor will not create giant wires
2017-06-13 16:58:22 -07:00
Colin Schmidt
8264c0a77e
add a debug print for xbar id mappings
2017-06-13 16:58:21 -07:00
Henry Cook
8278d22fcd
Merge pull request #776 from freechipsproject/lazy-raw-module-imp
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Use LazyMultiIOModuleImp to simplify top-level traits
2017-06-13 15:50:12 -07:00
Henry Cook
80a3278139
travis: travis_wait to 80
2017-06-13 14:24:40 -07:00
Henry Cook
9bbde9767c
rocketchip: top-level systems are now multi-IO modules
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Cake pattern only 2 layers instead of 3.
Standardized naming convention.
Comments for periphery mix-ins.
Testharnesses use new periphery helper methods.
2017-06-13 13:55:45 -07:00
Henry Cook
2e8a40a23f
diplomacy: Allow LazyModuleImps to be based on RawModules or MultiIOModules
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And add a MonitorBase class to be connect's return type.
2017-06-13 13:55:27 -07:00
Andrew Waterman
4a24e9a6c6
Merge pull request #792 from freechipsproject/fix-fdiv
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Fix FPU control bug for div/sqrt
2017-06-09 18:27:19 -07:00
Andrew Waterman
76af15a6ff
Fix FPU control bug for div/sqrt
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I was examining a WB-stage control signal instead of a MEM-stage control
signal. I refactored the code to group the signals together, so that this
sort of bug is less likely going forward.
2017-06-09 15:51:06 -07:00
Andrew Waterman
e69badb205
Merge pull request #791 from freechipsproject/tlb
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Fix I$ reset regression
2017-06-09 15:49:25 -07:00
Andrew Waterman
8552c77972
Fix I$ reset regression FU-357
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Can't rely on s2 TLB response, so mask using s2_valid.
2017-06-09 00:48:24 -07:00
Jack Koenig
0812f9387d
Bump firrtl to get performance bug fixes ( #790 )
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Other new features include version bumping, _RAND instead of _GEN for
termporary variables used for randomization, and printing the full
runtime.
2017-06-08 17:39:21 -04:00
Andrew Waterman
5a4daebbcc
minNum -> minimumNumber ( #766 )
2017-06-08 11:12:52 -07:00
Andrew Waterman
8cb250cfe6
Fix FMUL sign, again ( #789 )
2017-06-08 01:50:00 -07:00
Leway Colin
60c896b48c
Typo: is should be if ? ( #786 )
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Typo: is should be if ?
2017-06-07 10:40:13 -07:00
Andrew Waterman
d45fc0d670
Merge pull request #785 from freechipsproject/fmul-fix
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Fix FMUL sign of zero
2017-06-06 00:46:03 -07:00
Megan Wachs
f0a59a81c8
Merge pull request #783 from freechipsproject/plusarg_docstring
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plusarg_reader : Add the ability to add a documentation string.
2017-06-05 18:21:07 -07:00
Andrew Waterman
07ad9203ff
Fix FMUL sign of zero
2017-06-05 17:35:42 -07:00
Megan Wachs
8d2e9a8631
Merge remote-tracking branch 'origin/master' into plusarg_docstring
2017-06-05 17:23:44 -07:00
Wesley W. Terpstra
87a5665e43
axi4: only block writes if SAME master has outstanding reads ( #782 )
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* axi4: only block writes if SAME master has outstanding reads
* tilelink2: ToAXI4 rename variable
TL uses sources, not IDs like AXI. Keep it less confusing.
* tilelink2: ToAXI4 improve stall circuit delay
Don't bother decoding the AXI ID to compute stall.
2017-06-05 16:54:00 -07:00
