266a2f24bd
Disable Mul early out by default if XLen == 32
...
With a default unroll of 8, it doesn't help performance, but costs area.
2016-09-12 16:50:08 -07:00
96185e4b16
tighten an assert condition
...
dcache.s1_kill is a don't-care if dcache.req.valid wasn't previously high
2016-09-12 16:49:46 -07:00
beb141a20b
Allow M, A, D, C extensions to be disabled in misa register
2016-09-12 16:49:46 -07:00
f3cdeb08c6
pass nMemChannels to coreplex through CoreplexConfig
2016-09-12 12:40:10 -07:00
9d9f90646d
allow configuration of simulation memory latency
2016-09-12 12:33:50 -07:00
a21b04a7c1
playground for making different DAGs to use as DUTs
2016-09-12 10:32:45 -07:00
0671d5d637
Initial version of fuzzer and simple ram fuzz test
2016-09-12 10:32:45 -07:00
7760459b76
tilelink2 RegisterRouter: add RegField test patterns
2016-09-12 10:32:25 -07:00
85ae77c108
tilelink2 RAMModule: carefully stage the pipeline to make BRAMs possible
2016-09-12 10:32:25 -07:00
9560df537c
tilelink2 RegisterRouter: allow sub-4k devices in order to make useful unit tests
2016-09-12 10:32:24 -07:00
26f9e2dfbd
tilelink2 Parameters: fix width=1 address truncation bug
2016-09-12 10:32:24 -07:00
98a4facac7
tilelink2 RAMModel: clear Mems on power-up
2016-09-12 10:32:24 -07:00
17f7ab18de
tilelink2 RAMModel: model the state a RAM would have for Put+Gets
2016-09-12 10:32:24 -07:00
488b93d146
tilelink2 Parameters: if you support PutPartial, you must support PutFull
2016-09-12 10:32:24 -07:00
d6261e8ce8
tilelink2 Edge: add a numBeats1 method for predecremented code
2016-09-12 10:32:24 -07:00
5604049927
tilelink2 Buffer: support an unlimited number of channels
2016-09-12 10:32:24 -07:00
d985cdfc66
Merge branch 'master' into refactor-periphery
2016-09-10 23:42:13 -07:00
fea31c7061
let GlobalAddrMap and ConfigString overridable
2016-09-10 23:39:44 -07:00
bb3f514e8d
now able to add periphery devices through traits
...
Unfortunately, I had to touch a lot of code, which weren't quite possible to split up into multiple commits.
This commit gets rid of the "extra" infrastructure to add periphery devices into Top.
2016-09-10 23:39:29 -07:00
77e4aa63f8
Get rid of the unecessary Parameters for Async Reset Reg
2016-09-09 16:24:35 -07:00
b695ab5292
Merge branch 'master' into tweaks
2016-09-09 15:04:21 -07:00
5f5989848c
Merge remote-tracking branch 'origin/master' into black_box_regs
2016-09-09 13:12:52 -07:00
656aa78f7d
Pipeline FMAs more deeply by default
...
Rocket's QoR has improved enough that the FMAs are on the critical
path. This change seems to keep the integer pipeline's logic
paths balanced with the FPU.
2016-09-09 11:06:42 -07:00
eaa4b04ee5
Check D$ store->load collisions more precisely
...
Tolerate, for example, a half-word store and a half-word load to
different halves of the same word.
2016-09-09 11:06:42 -07:00
c28ca37944
tilelink2: get rid of fragile implicit lazyModule pattern, and support :=
...
We can more reliably find the current LazyModule from the LazyModule.stack
2016-09-08 23:06:59 -07:00
b587a409a3
tilelink2 Node: make it possible for {Identity,Output,Input}Node to pass a Vec
...
In order to implement a pass-through RAM Monitor model, we will want to support
a variable number of inputs and outputs with BOTH different manager and client
parameters on each bundle.
2016-09-08 21:34:20 -07:00
48ca478578
Merge branch 'master' into intbar
2016-09-08 21:09:59 -07:00
808a7f60f4
tilelink2 Legacy: it's only an error if it's valid ( #264 )
2016-09-08 21:09:40 -07:00
fda4c2bd76
Add a way to create Async Reset Registers and a way to easily access them with TL2
2016-09-08 20:02:07 -07:00
c1eb1f12a2
tilelink2: Rename GPIO to Example to avoid conflicts with real GPIO devices
2016-09-08 20:02:07 -07:00
cbf0670156
tilelink2 Legacy: it's only an error if it's valid
2016-09-08 19:32:00 -07:00
1b07d53f70
tilelink2 IntNodes: record interrupt ranges in parameters
2016-09-08 18:51:43 -07:00
66f58cf2d0
tilelink2 RegisterRouter: support new TL2 interrupts
2016-09-08 15:25:50 -07:00
23e896ed5d
tilelink2 IntNodes: support interrupt graphs
2016-09-08 15:25:48 -07:00
d7df7d3109
tilelink2: connect Nodes to LazyModules for better error messages
2016-09-08 15:24:04 -07:00
53987cd9d4
tilelink2 Nodes: support non-Bundle data for io type
2016-09-08 15:19:12 -07:00
60a503dc2f
tilelink2 RegField: add a w1ToClear RegField
2016-09-08 14:02:49 -07:00
99b7e734cd
tilelink2 Bundles: fix wrong sink width!
2016-09-08 13:47:40 -07:00
9bfd8c1cf5
TL2 WidthWidget ( #258 )
...
* tilelink2 Narrower: support widenening and narrowing on all channels
Be extra careful with the mask transformations
We need to make sure that narrowing or widening do not cause a loss
of information about the operation. The addr_hi+(mask|addr_lo) conversions
are now 1-1, except on D, which should not matter.
* tilelink2 SRAM: work around firrtl SeqMem bug
* tilelink2 WidthWidget: renamed from Narrower (it now converts both ways)
* tilelink2 mask: fix an issue with width=1 data buses
2016-09-08 10:38:38 -07:00
2c000a99da
compartmentalize Top into periphery traits
2016-09-08 02:08:57 -07:00
e35e7b2ee3
Fix routing in non-contiguous MMIO regions
...
This is a temporary fix, which can generate more hardware than necessary, but this is OK for now, since this code will soon be replaced with tilelink2 code.
2016-09-07 19:28:12 -07:00
7603b86239
Merge branch 'master' into use-companion
2016-09-07 12:56:55 -07:00
254f49093c
only use companion objects for types
2016-09-07 12:32:34 -07:00
23d0b31615
Merge branch 'master' into tilelink2.2
2016-09-07 11:47:50 -07:00
02a2439222
Support a degenerate PLIC with no interrupts
...
Resolves #249
2016-09-07 11:21:13 -07:00
70cfd7ce13
Make DefaultRV32Config be RV32IMAFCS, not RV32IMC
...
The latter is more the domain of TinyConfig.
2016-09-07 01:58:25 -07:00
a7f47f3c23
Reduce default BTB size
...
The old value 62 seems to have been a typo introduced over 2 years ago
in commit 63bd0b9d2a
2016-09-07 01:51:27 -07:00
9fea4c83da
Add RV32F support
2016-09-07 00:05:39 -07:00
66e9f027e0
Add MuxT to mux on Tuple2 and Tuple3
2016-09-07 00:05:38 -07:00
511cc6c5c5
Evaluate arg to Boolean.option lazily
2016-09-07 00:05:38 -07:00
