540502f96d
Convert frontend and icache to diplomacy/tl2 ( #486 )
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* [rocket] file capitalization
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
2016-12-12 17:38:55 -08:00
531f3684ed
Removing module list for merging. (will need to create iterator in future)
2016-12-12 16:25:31 -08:00
aae9b23036
Update with paratermized LazyModule
2016-12-12 16:16:56 -08:00
762afcd54a
Merge remote-tracking branch 'origin/master' into jchang_test
2016-12-09 16:56:49 -08:00
4c3083c181
Remove unnecessary val
2016-12-09 16:44:30 -08:00
09afbbafdb
ahb: weaken RegisterRouter assertion
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As written I think it could potentially fail, but what I actually care
about is something weaker that should be true. Assert: nothing lost.
2016-12-08 18:00:39 -08:00
588b944ed4
ahb: implement and test address decoding
2016-12-08 18:00:39 -08:00
5d1064fcb1
ahb: include a unit test
2016-12-08 18:00:39 -08:00
51dfb9cb06
ahb: TileLink master
2016-12-08 18:00:39 -08:00
01b0f6a52b
ahb: new diplomacy-based AHB bus definition
2016-12-08 18:00:39 -08:00
54cc071a64
Fix Fragmenter to ensure logical operations must be sent out atomically.
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Edited Fuzzer so that it can generate infinite operations when nOperations is net to 0
2016-12-07 16:22:05 -08:00
c2eedbfe23
tilelink2 Monitor: use Parameters instead of global variables
2016-12-07 12:24:03 -08:00
020fbe8be9
diplomacy: make config.Parameters available in bundle connect()
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This makes it posisble to use Parameters to control Monitors.
However, we need to make all LazyModules carry Parameters.
2016-12-07 12:24:01 -08:00
915697cb09
Fix FEQ flag generation ( #479 )
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FEQ is not a signaling comparison (i.e., qNaN is not an invalid input).
Also, minor code cleanup.
2016-12-06 11:54:29 -08:00
fbfa15efea
TLBroadcast: support non-FIFO devices ( #482 )
2016-12-05 22:10:37 -08:00
3c9718ec8f
clint: undefined registers must be zero ( #480 )
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This is needed so that SMP-safe boot loaders can safely
read/write to the IPI register of non-existent harts.
2016-12-05 17:11:53 -08:00
f3d0692619
Make a directory for the config package ( #464 )
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* [config] make dir structure mirror packages
* [config] expunge max_int
2016-12-05 10:42:16 -08:00
d0a0c887dc
[tracegen] decrease default address bag size ( #462 )
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while increasing the default number of requests.
2016-12-04 22:46:55 -08:00
36fe024671
CacheName no longer needed in RoCCInterface
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With dcacheParams passed to a RoCC, the CacheName no longer needs to be
specified.
2016-12-04 19:01:39 -08:00
624db2034b
Make instantiated RoCC use dcacheParams
2016-12-04 19:01:39 -08:00
cff2612cdb
minor Changes needed to support formal tests
2016-12-01 15:02:23 -08:00
b7963eca4e
copyright: ran scripts/modify-copyright
2016-11-27 22:15:43 -08:00
e2ec1d00ad
copyright: normalize /// to // in comments
2016-11-27 22:15:43 -08:00
a0e10aec05
uncore: removed obsolete Builder file
2016-11-27 22:15:43 -08:00
4146f6a792
TLB: do not access illegal addresses ( #460 )
2016-11-26 15:11:42 -08:00
a17753983a
coreplex: allow legacy devices to override the config string ( #458 )
2016-11-25 19:38:24 -08:00
233280e7d2
AsyncBundle: save a wasted bit when depth=1
2016-11-25 18:11:01 -08:00
d755edffcc
DebugTransport: use ToAsyncDebugBus for correct depth
2016-11-25 18:10:28 -08:00
2b80386a9e
rocketchip: TileInterrupts needs a TLCacheEdge ( #456 )
2016-11-25 17:02:29 -08:00
1e0aca7358
dcache: the high bit of s2_req.typ is the SIGN bit (not size) ( #455 )
2016-11-25 15:26:22 -08:00
0baa1c9a45
coreplex: CacheBlockOffsetBits was wrong!
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This bug is ancient. I don't understand how it never mattered before.
Anyway, in processors with a custom CacheBlockBytes, this value is wrong!
The symptom is that TL1 components end up missing high address bits.
This causes, for example, a system to jump to 0 instead of RAM.
I don't understand how this very serious bug did not cause problems before.
2016-11-24 18:32:44 -08:00
a670f63c81
periphery: a handy trait to turn-off ExtMem
2016-11-23 20:44:45 -08:00
30e890b480
diplomacy: include InternalNodes for AXI4 and TL
2016-11-23 20:44:45 -08:00
9f1c668c4f
config: when modifying Parameters, subordinate lookups use top
2016-11-23 20:44:45 -08:00
566cc9e60b
rocketchip: RTCPeriod config
2016-11-23 20:44:45 -08:00
e87f54d4f7
rocketchip: traits for adding external TL2 ports
2016-11-23 20:44:42 -08:00
4b9dc78951
rocketchip: add a parameter-controlled debug port
2016-11-23 15:35:53 -08:00
38c5af5bad
[rocket] cleanup mshr logic
2016-11-23 12:09:56 -08:00
dae6772624
factor out common cache subcomponents into uncore.util
2016-11-23 12:09:35 -08:00
c65c255815
[coreplex] TileId moved to groundtest
2016-11-23 12:08:45 -08:00
1d3cad3671
tilelink2 SourceShrinker: handle degenerate cases for free
2016-11-22 22:17:30 -08:00
1e7d597fd3
rocketchip: don't waste too many sources on the AXI master port
2016-11-22 21:48:41 -08:00
c0b27999ea
tilelink2 SourceShrinker: a concurrency reducing adapter
2016-11-22 21:43:38 -08:00
0097274ea3
Broadcast: single-cycle response is possible
2016-11-22 20:45:40 -08:00
437be0f36a
PositionalMultiQueue: use a UInt instead of Reg(Vec(Bool))
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This results in much less Verilog to simulate
2016-11-22 20:39:38 -08:00
f9de7173cc
PositionalMultiQueue: use 1-write n-read Mem instead of Reg(Vec(...))
2016-11-22 18:46:11 -08:00
d9a203b0f0
PositionalMultiQueue: convert 'next' to a single write port
2016-11-22 18:38:55 -08:00
13190a5de0
rocketchip: re-add AXI4 interface
2016-11-22 17:27:58 -08:00
c230580157
coreplex: rename RocketPlex => RocketTiles
2016-11-22 17:27:58 -08:00
bbabcf67ff
coreplex: width adapter should happen as part of coherence manager
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In the future we will want the L2 to be wider on the backside so that
we can take advantage of fat DDR controllers (256bits/beat).
2016-11-22 17:27:58 -08:00
