1
0
Commit Graph

139 Commits

Author SHA1 Message Date
001d9821bd Merge remote-tracking branch 'origin/master' into tl2-tile 2016-11-18 18:19:41 -08:00
a6188efc41 rocketchip: break infinite Config loops 2016-11-18 16:18:33 -08:00
37a3c22639 rocketchip: move from using cde to config 2016-11-18 16:18:33 -08:00
30425d1665 rocketchip: eliminate all Knobs 2016-11-18 14:31:42 -08:00
bab504cc3f Add various granular and composable configs. 2016-11-18 11:30:07 -08:00
179c93db42 tilelink2 broadcast: make it controlled via Config 2016-11-17 17:26:49 -08:00
f4ca5ea1f3 rocketchip: match simulated memory width to ExtMem.beatBytes 2016-11-17 15:40:47 -08:00
12d0d8bea2 rocketchip: remove obsolete bus configuration 2016-11-17 14:30:15 -08:00
c82b371354 rocketchip: remove obsolete TL1 config 2016-11-17 14:24:45 -08:00
dfc3a0dafb tilelink2: do not depend on obsolete TL1 configuration 2016-11-17 14:07:53 -08:00
84f249bd03 [rocketchip] BigInt cast 2016-11-16 18:11:06 -08:00
408e78e35e rocketchip Periphery: ExtMem and ExtBus Configs 2016-11-16 16:50:30 -08:00
10e459fedb rocket: change connection between rocketchip and coreplex
* rtc and dtm are now crossed half-and-half on the two sides
* groundtest no longer uses riscv platform traits
2016-11-15 18:27:52 -08:00
385b5d5698 axi4: default should be GET_EFFECTS 2016-11-14 15:19:39 -08:00
32fd11935c rocketchip: use TL2 and AXI4 for memory subsytem 2016-11-04 13:36:47 -07:00
f943c5d6ef rocketchip: connect rtcTick to coreplex 2016-10-31 11:42:47 -07:00
aabd17d935 rocketchip: must create bundles within Module scope
1. Bundles be created after base class Module constructor runs
2. Bundles must be created before Module(...) runs

Solution: pass a bundle constructor to the cake base class

Require the constructor to take a parameter so people don't use it by
accident; they should get a type error.

Consistently name all the cake arguments with an _io, _coreplex, _outer,
so that they don't shadow the base class variables you should be using.
2016-10-31 11:42:47 -07:00
4de1822470 rocketchip: avoid using the nearly defunct GlobalAddrMap 2016-10-31 11:42:47 -07:00
688e1bffdf rocketchip: pull rtcTick out of the coreplex 2016-10-31 11:42:47 -07:00
5bca13ebdb rocketchip: use self-type constraints 2016-10-31 11:42:47 -07:00
d51b0b5c02 rocketchip: use self-type 2016-10-31 11:42:47 -07:00
ba529c3716 rocketchip: use TileLink2 interrupts 2016-10-31 11:42:47 -07:00
ac886026e6 rocketchip: reduce number of type parameters 2016-10-31 11:42:47 -07:00
72a7948ad2 rocketchip Periphery: move atomics before WidthWidget => 64-bit AMOs 2016-10-31 11:42:47 -07:00
e9725aea2f rocketchip: all of the address map now comes from TL2 2016-10-31 11:42:44 -07:00
401fd378b4 rocketchip: include devices from cbus in ConfigString 2016-10-31 11:42:13 -07:00
a73aa351ca rocketchip: fix all clock crossings 2016-10-31 11:42:13 -07:00
825c253a72 rocketchip: move TL2 and cake pattern into Coreplex 2016-10-31 11:42:13 -07:00
89139a9492 Plic: split constants from variables used in config string 2016-10-31 11:42:13 -07:00
f8a0829134 rocketchip: remove clint; it moves into coreplex 2016-10-31 11:42:13 -07:00
c3dacca39a rocketchip: remove pbus; TL2 has swallowed it completely 2016-10-31 11:42:08 -07:00
3df797fcab rocketchip: replace TL1 MMIO with an example of TL2 MMIO 2016-10-31 11:41:18 -07:00
ec2d23b8b7 rocketchip: Bundle-slices need access to the outer LazyModule
We need this change in order for some ports to use parameters that result
from LazyModule diplomacy.

Now you can eat your cake too!
2016-10-31 11:41:18 -07:00
0ae45d0f24 rocketchip: bundle (=> B) need not be delayed; Module is constructed later 2016-10-31 11:41:18 -07:00
0dbda2f07d rocketchip: remove obsolete pDevices used during TL1=>2 migration 2016-10-31 11:41:18 -07:00
67ab27f5a5 diplomacy: guess the LazyModule name from the containing class 2016-10-25 15:58:09 -07:00
7dc97674d6 rocketchip: include an socBus between l1tol2 and periphery (#415)
Sometimes we have high performance devices that go inbetween.
2016-10-24 23:56:09 -07:00
3a1d8fe482 debug: use a different form of the crossing which doesn't create an AsyncScope (#394) 2016-10-09 20:33:18 -07:00
1e69a2dc1c [tilelink2] allow TL monitors to be globally enabled or disabled (#392) 2016-10-09 12:34:10 -07:00
eddf1679f5 Use <> instead of := for bi-directional connections 2016-10-04 22:29:39 -07:00
f05298d9bc tilelink2: move general-purpose code out of tilelink2 package 2016-10-03 16:22:28 -07:00
0a4ef66894 BaseTop: record top module; more general than GraphML 2016-10-03 15:05:45 -07:00
28eba9b5ac clint/plic: Move the default addresses 2016-10-01 15:46:55 -07:00
2bdf8c2be7 Merge branch 'master' into move-to-util 2016-09-29 14:42:11 -07:00
ab3219cf6e don't use Scala to Chisel implicit conversions outside of rocket 2016-09-29 14:35:42 -07:00
9910c69c67 Move a bunch more things into util package
A lot of utility code was just being imported willy-nilly from one
package to another. This moves the common code into util to make things
more sensible. The code moved were

 * The AsyncQueue and AsyncDecoupledCrossing from junctions.
 * All of the code in rocket's util.scala
 * The BlackBox asynchronous reset registers from uncore.tilelink2
 * The implicit definitions from uncore.util
2016-09-29 14:23:42 -07:00
449d689a4e jtag: Connect the JTAG DTM side of the synchronizer! 2016-09-29 13:48:55 -07:00
0924f8adb0 print out assigned inerrupt ranges 2016-09-29 11:59:32 -07:00
4c3e8ec1b4 assign interrupt ranges deterministically 2016-09-29 11:59:32 -07:00
c45cc76cef Get rid of remaining MemIO code
The only thing we were still using it for was for the MIFDataBits
and MIFTagBits parameters. We replace these with EdgeDataBits and
EdgeIDBits.
2016-09-27 16:28:17 -07:00