2011-10-26 08:02:47 +02:00
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package Top {
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import Chisel._
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import Node._;
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import Constants._
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import Instructions._
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2011-11-10 09:23:29 +01:00
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class ioDpathDmem extends Bundle()
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{
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2012-01-24 09:15:17 +01:00
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val req_addr = UFix(VADDR_BITS+1, OUTPUT);
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2012-01-18 19:28:48 +01:00
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val req_tag = UFix(CPU_TAG_BITS, OUTPUT);
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val req_data = Bits(64, OUTPUT);
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val resp_val = Bool(INPUT);
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val resp_miss = Bool(INPUT);
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val resp_replay = Bool(INPUT);
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val resp_tag = Bits(CPU_TAG_BITS, INPUT);
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val resp_data = Bits(64, INPUT);
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val resp_data_subword = Bits(64, INPUT);
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2011-11-10 09:23:29 +01:00
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}
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2011-11-10 06:54:11 +01:00
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class ioDpathImem extends Bundle()
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{
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2012-01-24 09:15:17 +01:00
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val req_addr = UFix(VADDR_BITS+1, OUTPUT);
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2012-01-18 19:28:48 +01:00
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val resp_data = Bits(32, INPUT);
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2011-11-10 06:54:11 +01:00
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}
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2011-10-26 08:02:47 +02:00
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class ioDpathAll extends Bundle()
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{
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val host = new ioHost();
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2011-11-02 01:59:27 +01:00
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val ctrl = new ioCtrlDpath().flip();
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2011-12-01 07:51:59 +01:00
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val console = new ioConsole(List("valid","bits"));
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2011-10-26 08:02:47 +02:00
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val debug = new ioDebug();
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2011-11-10 09:23:29 +01:00
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val dmem = new ioDpathDmem();
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2011-11-10 06:54:11 +01:00
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val imem = new ioDpathImem();
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2012-01-18 19:28:48 +01:00
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val ptbr_wen = Bool(OUTPUT);
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val ptbr = UFix(PADDR_BITS, OUTPUT);
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2012-02-08 08:54:25 +01:00
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val fpu = new ioDpathFPU();
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2011-10-26 08:02:47 +02:00
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}
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class rocketDpath extends Component
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{
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val io = new ioDpathAll();
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2011-11-10 20:26:13 +01:00
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val btb = new rocketDpathBTB(8); // # of entries in BTB
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2011-10-26 08:02:47 +02:00
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val if_btb_target = btb.io.target;
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val pcr = new rocketDpathPCR();
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val ex_pcr = pcr.io.r.data;
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val alu = new rocketDpathALU();
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val ex_alu_out = alu.io.out;
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2012-01-02 02:04:14 +01:00
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val ex_alu_adder_out = alu.io.adder_out;
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2011-10-26 08:02:47 +02:00
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val div = new rocketDivider(64);
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val div_result = div.io.div_result_bits;
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val div_result_tag = div.io.div_result_tag;
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val div_result_val = div.io.div_result_val;
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val mul = new rocketMultiplier();
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val mul_result = mul.io.result;
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val mul_result_tag = mul.io.result_tag;
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val mul_result_val = mul.io.result_val;
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2011-12-01 06:54:55 +01:00
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val rfile = new rocketDpathRegfile();
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2011-10-26 08:02:47 +02:00
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// instruction fetch definitions
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2012-01-24 09:15:17 +01:00
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val if_reg_pc = Reg(resetVal = UFix(START_ADDR,VADDR_BITS+1));
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2011-10-26 08:02:47 +02:00
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// instruction decode definitions
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2011-11-09 23:52:17 +01:00
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val id_reg_valid = Reg(resetVal = Bool(false));
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2011-11-02 01:59:27 +01:00
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val id_reg_inst = Reg(resetVal = NOP);
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2012-01-24 09:15:17 +01:00
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val id_reg_pc = Reg() { UFix(width = VADDR_BITS+1) };
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2011-10-26 08:02:47 +02:00
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// execute definitions
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2011-11-04 23:40:41 +01:00
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val ex_reg_valid = Reg(resetVal = Bool(false));
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2012-01-02 01:09:40 +01:00
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val ex_reg_pc = Reg() { UFix() };
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val ex_reg_inst = Reg() { Bits() };
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val ex_reg_raddr2 = Reg() { UFix() };
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val ex_reg_rs2 = Reg() { Bits() };
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val ex_reg_rs1 = Reg() { Bits() };
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val ex_reg_waddr = Reg() { UFix() };
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val ex_reg_ctrl_sel_alu2 = Reg() { UFix() };
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val ex_reg_ctrl_sel_alu1 = Reg() { UFix() };
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2011-11-18 08:50:45 +01:00
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val ex_reg_ctrl_eret = Reg(resetVal = Bool(false));
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2012-01-02 01:09:40 +01:00
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val ex_reg_ctrl_fn_dw = Reg() { UFix() };
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val ex_reg_ctrl_fn_alu = Reg() { UFix() };
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2011-11-02 01:59:27 +01:00
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val ex_reg_ctrl_ll_wb = Reg(resetVal = Bool(false));
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val ex_reg_ctrl_mul_val = Reg(resetVal = Bool(false));
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2012-01-02 01:09:40 +01:00
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val ex_reg_ctrl_mul_fn = Reg() { UFix() };
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2011-11-02 01:59:27 +01:00
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val ex_reg_ctrl_div_val = Reg(resetVal = Bool(false));
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2012-01-02 01:09:40 +01:00
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val ex_reg_ctrl_div_fn = Reg() { UFix() };
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val ex_reg_ctrl_sel_wb = Reg() { UFix() };
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2011-11-02 01:59:27 +01:00
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val ex_reg_ctrl_ren_pcr = Reg(resetVal = Bool(false));
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val ex_reg_ctrl_wen_pcr = Reg(resetVal = Bool(false));
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val ex_wdata = Wire() { Bits() };
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2011-11-02 03:05:27 +01:00
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// memory definitions
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2011-11-04 23:40:41 +01:00
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val mem_reg_valid = Reg(resetVal = Bool(false));
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2012-01-02 01:09:40 +01:00
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val mem_reg_pc = Reg() { UFix() };
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val mem_reg_waddr = Reg() { UFix() };
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val mem_reg_wdata = Reg() { Bits() };
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val mem_reg_raddr2 = Reg() { UFix() };
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2011-11-02 21:32:32 +01:00
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val mem_reg_ctrl_ll_wb = Reg(resetVal = Bool(false));
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2012-01-03 00:42:39 +01:00
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val mem_reg_ctrl_mul_val = Reg(resetVal = Bool(false));
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val mem_reg_ctrl_div_val = Reg(resetVal = Bool(false));
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2011-11-02 01:59:27 +01:00
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val mem_reg_ctrl_wen_pcr = Reg(resetVal = Bool(false));
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2012-02-07 02:26:45 +01:00
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val mem_wdata = Wire() { Bits() };
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2011-11-02 01:59:27 +01:00
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2011-11-02 03:05:27 +01:00
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// writeback definitions
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2012-01-18 06:12:31 +01:00
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val wb_reg_valid = Reg(resetVal = Bool(false));
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2012-01-03 00:42:39 +01:00
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val wb_reg_pc = Reg() { UFix() };
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2012-01-02 01:09:40 +01:00
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val wb_reg_waddr = Reg() { UFix() };
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val wb_reg_wdata = Reg() { Bits() };
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2012-01-03 00:42:39 +01:00
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val wb_reg_raddr2 = Reg() { UFix() };
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2011-11-02 01:59:27 +01:00
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val wb_reg_ctrl_ll_wb = Reg(resetVal = Bool(false));
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2012-01-03 00:42:39 +01:00
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val wb_reg_ctrl_wen_pcr = Reg(resetVal = Bool(false));
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2012-02-02 00:36:01 +01:00
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val wb_wdata = Wire() { Bits() };
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2011-11-02 01:59:27 +01:00
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2012-01-02 11:51:30 +01:00
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val r_dmem_resp_replay = Reg(resetVal = Bool(false));
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2012-02-08 08:54:25 +01:00
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val r_dmem_fp_replay = Reg(resetVal = Bool(false));
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2012-01-02 01:09:40 +01:00
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val r_dmem_resp_waddr = Reg() { UFix() };
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2011-11-02 03:05:27 +01:00
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2011-10-26 08:02:47 +02:00
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// instruction fetch stage
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2011-11-09 23:52:17 +01:00
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val if_pc_plus4 = if_reg_pc + UFix(4);
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2011-10-26 08:02:47 +02:00
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2012-02-02 22:33:27 +01:00
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val ex_pc_plus4 = ex_reg_pc + UFix(4);
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2011-10-26 08:02:47 +02:00
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val ex_sign_extend =
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Cat(Fill(52, ex_reg_inst(21)), ex_reg_inst(21,10));
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val ex_sign_extend_split =
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Cat(Fill(52, ex_reg_inst(31)), ex_reg_inst(31,27), ex_reg_inst(16,10));
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val branch_adder_rhs =
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2012-01-24 09:15:17 +01:00
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Mux(io.ctrl.ex_jmp, Cat(Fill(VADDR_BITS-25, ex_reg_inst(31)), ex_reg_inst(31,7), UFix(0,1)),
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Cat(ex_sign_extend_split(VADDR_BITS-1,0), UFix(0, 1)));
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2011-10-26 08:02:47 +02:00
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val ex_branch_target = ex_reg_pc + branch_adder_rhs.toUFix;
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2012-01-24 09:15:17 +01:00
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val ex_jr_target_sign = Mux(ex_alu_adder_out(VADDR_BITS-1), ~ex_alu_adder_out(63,VADDR_BITS) === UFix(0), ex_alu_adder_out(63,VADDR_BITS) != UFix(0))
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val ex_jr_target_extended = Cat(ex_jr_target_sign, ex_alu_adder_out(VADDR_BITS-1,0)).toUFix
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val jr_br_target = Mux(io.ctrl.ex_jr, ex_jr_target_extended, ex_branch_target);
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2012-01-02 11:51:30 +01:00
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btb.io.correct_target := jr_br_target
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2011-10-26 08:02:47 +02:00
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val if_next_pc =
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2012-01-24 09:15:17 +01:00
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Mux(io.ctrl.sel_pc === PC_BTB, Cat(if_btb_target(VADDR_BITS-1), if_btb_target),
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2012-02-02 22:33:27 +01:00
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Mux(io.ctrl.sel_pc === PC_EX4, ex_pc_plus4,
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2011-11-10 09:50:09 +01:00
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Mux(io.ctrl.sel_pc === PC_BR, ex_branch_target,
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2012-01-24 09:15:17 +01:00
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Mux(io.ctrl.sel_pc === PC_JR, ex_jr_target_extended,
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Mux(io.ctrl.sel_pc === PC_PCR, wb_reg_wdata(VADDR_BITS,0), // only used for ERET
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Mux(io.ctrl.sel_pc === PC_EVEC, Cat(pcr.io.evec(VADDR_BITS-1), pcr.io.evec),
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2012-01-18 06:12:31 +01:00
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Mux(io.ctrl.sel_pc === PC_WB, wb_reg_pc,
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2011-12-10 04:42:58 +01:00
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if_pc_plus4))))))); // PC_4
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2011-11-10 12:38:59 +01:00
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2012-01-12 02:49:32 +01:00
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when (!io.ctrl.stallf) {
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2011-11-18 08:50:45 +01:00
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if_reg_pc <== if_next_pc.toUFix;
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2011-10-26 08:02:47 +02:00
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}
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2011-11-18 08:50:45 +01:00
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2012-01-24 09:15:17 +01:00
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io.ctrl.xcpt_ma_inst := if_next_pc(1,0) != Bits(0)
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2011-11-10 12:38:59 +01:00
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2011-10-26 08:02:47 +02:00
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io.imem.req_addr :=
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Mux(io.ctrl.stallf, if_reg_pc,
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2011-11-18 08:50:45 +01:00
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if_next_pc.toUFix);
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2011-10-26 08:02:47 +02:00
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btb.io.current_pc4 := if_pc_plus4;
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2012-01-23 18:51:35 +01:00
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btb.io.hit <> io.ctrl.btb_hit;
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btb.io.wen <> io.ctrl.wen_btb;
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btb.io.clr <> io.ctrl.clr_btb;
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2012-02-02 22:33:27 +01:00
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btb.io.correct_pc4 := ex_pc_plus4;
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2012-01-02 11:51:30 +01:00
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io.ctrl.btb_match := id_reg_pc === jr_br_target;
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2011-10-26 08:02:47 +02:00
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// instruction decode stage
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when (!io.ctrl.stalld) {
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id_reg_pc <== if_reg_pc;
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when(io.ctrl.killf) {
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2011-11-04 23:40:41 +01:00
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id_reg_inst <== NOP;
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id_reg_valid <== Bool(false);
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2011-10-26 08:02:47 +02:00
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}
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otherwise {
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2011-11-04 23:40:41 +01:00
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id_reg_inst <== io.imem.resp_data;
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id_reg_valid <== Bool(true);
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2011-10-26 08:02:47 +02:00
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}
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}
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val id_raddr1 = id_reg_inst(26,22).toUFix;
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val id_raddr2 = id_reg_inst(21,17).toUFix;
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// regfile read
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2012-01-23 18:51:35 +01:00
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rfile.io.r0.en <> io.ctrl.ren2;
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2011-10-26 08:02:47 +02:00
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rfile.io.r0.addr := id_raddr2;
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val id_rdata2 = rfile.io.r0.data;
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2012-01-23 18:51:35 +01:00
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rfile.io.r1.en <> io.ctrl.ren1;
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2011-10-26 08:02:47 +02:00
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rfile.io.r1.addr := id_raddr1;
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val id_rdata1 = rfile.io.r1.data;
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2011-11-02 01:59:27 +01:00
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// destination register selection
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2012-01-02 11:51:30 +01:00
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val id_ctrl_ll_wb = io.ctrl.div_wb || io.ctrl.mul_wb || r_dmem_resp_replay;
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2011-10-26 08:02:47 +02:00
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val id_waddr =
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2012-01-02 11:51:30 +01:00
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Mux(r_dmem_resp_replay, r_dmem_resp_waddr,
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2011-10-26 08:02:47 +02:00
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Mux(io.ctrl.mul_wb, mul_result_tag,
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2012-01-02 11:51:30 +01:00
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Mux(io.ctrl.div_wb, div_result_tag,
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2011-10-26 08:02:47 +02:00
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Mux(io.ctrl.sel_wa === WA_RD, id_reg_inst(31,27).toUFix,
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Mux(io.ctrl.sel_wa === WA_RA, RA,
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2012-01-02 11:51:30 +01:00
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UFix(0, 5))))));
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2011-10-26 08:02:47 +02:00
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2011-11-02 01:59:27 +01:00
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// bypass muxes
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2011-10-26 08:02:47 +02:00
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val id_rs1 =
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2012-01-02 11:51:30 +01:00
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Mux(r_dmem_resp_replay, io.dmem.resp_data_subword,
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2011-10-26 08:02:47 +02:00
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Mux(io.ctrl.div_wb, div_result,
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Mux(io.ctrl.mul_wb, mul_result,
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2012-02-08 08:54:25 +01:00
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Mux(id_raddr1 != UFix(0, 5) && (io.ctrl.ex_wen || ex_reg_ctrl_ll_wb) && id_raddr1 === ex_reg_waddr, ex_wdata,
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Mux(id_raddr1 != UFix(0, 5) && (io.ctrl.mem_wen || mem_reg_ctrl_ll_wb) && id_raddr1 === mem_reg_waddr, mem_wdata,
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Mux(id_raddr1 != UFix(0, 5) && (io.ctrl.wb_wen || wb_reg_ctrl_ll_wb) && id_raddr1 === wb_reg_waddr, wb_wdata,
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2012-02-07 02:26:45 +01:00
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id_rdata1))))));
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2011-10-26 08:02:47 +02:00
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val id_rs2 =
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2012-02-08 08:54:25 +01:00
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Mux(id_raddr2 != UFix(0, 5) && (io.ctrl.ex_wen || ex_reg_ctrl_ll_wb) && id_raddr2 === ex_reg_waddr, ex_wdata,
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Mux(id_raddr2 != UFix(0, 5) && (io.ctrl.mem_wen || mem_reg_ctrl_ll_wb) && id_raddr2 === mem_reg_waddr, mem_wdata,
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Mux(id_raddr2 != UFix(0, 5) && (io.ctrl.wb_wen || wb_reg_ctrl_ll_wb) && id_raddr2 === wb_reg_waddr, wb_wdata,
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2012-02-07 02:26:45 +01:00
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id_rdata2)));
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2011-10-26 08:02:47 +02:00
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2011-11-02 01:59:27 +01:00
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io.ctrl.inst := id_reg_inst;
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2011-10-26 08:02:47 +02:00
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// execute stage
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ex_reg_pc <== id_reg_pc;
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ex_reg_inst <== id_reg_inst;
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ex_reg_raddr2 <== id_raddr2;
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ex_reg_rs2 <== id_rs2;
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ex_reg_rs1 <== id_rs1;
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ex_reg_waddr <== id_waddr;
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ex_reg_ctrl_sel_alu2 <== io.ctrl.sel_alu2;
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|
ex_reg_ctrl_sel_alu1 <== io.ctrl.sel_alu1.toUFix;
|
|
|
|
ex_reg_ctrl_fn_dw <== io.ctrl.fn_dw.toUFix;
|
|
|
|
ex_reg_ctrl_fn_alu <== io.ctrl.fn_alu;
|
|
|
|
ex_reg_ctrl_mul_fn <== io.ctrl.mul_fn;
|
|
|
|
ex_reg_ctrl_div_fn <== io.ctrl.div_fn;
|
2012-01-02 11:51:30 +01:00
|
|
|
ex_reg_ctrl_ll_wb <== id_ctrl_ll_wb;
|
2011-10-26 08:02:47 +02:00
|
|
|
ex_reg_ctrl_sel_wb <== io.ctrl.sel_wb;
|
|
|
|
ex_reg_ctrl_ren_pcr <== io.ctrl.ren_pcr;
|
|
|
|
|
|
|
|
when(io.ctrl.killd) {
|
2011-11-04 23:40:41 +01:00
|
|
|
ex_reg_valid <== Bool(false);
|
2011-10-26 08:02:47 +02:00
|
|
|
ex_reg_ctrl_div_val <== Bool(false);
|
|
|
|
ex_reg_ctrl_mul_val <== Bool(false);
|
|
|
|
ex_reg_ctrl_wen_pcr <== Bool(false);
|
|
|
|
ex_reg_ctrl_eret <== Bool(false);
|
|
|
|
}
|
|
|
|
otherwise {
|
2011-11-04 23:40:41 +01:00
|
|
|
ex_reg_valid <== id_reg_valid;
|
2011-10-26 08:02:47 +02:00
|
|
|
ex_reg_ctrl_div_val <== io.ctrl.div_val;
|
|
|
|
ex_reg_ctrl_mul_val <== io.ctrl.mul_val;
|
|
|
|
ex_reg_ctrl_wen_pcr <== io.ctrl.wen_pcr;
|
2011-11-18 08:50:45 +01:00
|
|
|
ex_reg_ctrl_eret <== io.ctrl.id_eret;
|
2011-10-26 08:02:47 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
val ex_alu_in2 =
|
|
|
|
Mux(ex_reg_ctrl_sel_alu2 === A2_SEXT, ex_sign_extend,
|
|
|
|
Mux(ex_reg_ctrl_sel_alu2 === A2_SPLIT, ex_sign_extend_split,
|
|
|
|
Mux(ex_reg_ctrl_sel_alu2 === A2_RS2, ex_reg_rs2,
|
2012-01-02 06:28:38 +01:00
|
|
|
UFix(0, 64)))); // A2_0
|
2011-10-26 08:02:47 +02:00
|
|
|
|
|
|
|
val ex_alu_in1 =
|
|
|
|
Mux(ex_reg_ctrl_sel_alu1 === A1_RS1, ex_reg_rs1,
|
2012-01-02 06:28:38 +01:00
|
|
|
Cat(Fill(32, ex_reg_inst(26)),ex_reg_inst(26,7),UFix(0, 12))); // A1_LUI
|
2011-10-26 08:02:47 +02:00
|
|
|
|
|
|
|
val ex_alu_shamt =
|
|
|
|
Cat(ex_alu_in2(5) & ex_reg_ctrl_fn_dw === DW_64, ex_alu_in2(4,0)).toUFix;
|
|
|
|
|
|
|
|
alu.io.dw := ex_reg_ctrl_fn_dw;
|
|
|
|
alu.io.fn := ex_reg_ctrl_fn_alu;
|
|
|
|
alu.io.shamt := ex_alu_shamt.toUFix;
|
|
|
|
alu.io.in2 := ex_alu_in2.toUFix;
|
|
|
|
alu.io.in1 := ex_alu_in1.toUFix;
|
|
|
|
|
|
|
|
// divider
|
2011-12-20 01:57:53 +01:00
|
|
|
div.io.dw := ex_reg_ctrl_fn_dw;
|
2011-10-26 08:02:47 +02:00
|
|
|
div.io.div_fn := ex_reg_ctrl_div_fn;
|
2012-01-03 00:42:39 +01:00
|
|
|
div.io.div_val := ex_reg_ctrl_div_val;
|
|
|
|
div.io.div_kill := mem_reg_ctrl_div_val && io.ctrl.killm;
|
2011-10-26 08:02:47 +02:00
|
|
|
div.io.div_waddr := ex_reg_waddr;
|
|
|
|
div.io.dpath_rs1 := ex_reg_rs1;
|
|
|
|
div.io.dpath_rs2 := ex_reg_rs2;
|
|
|
|
div.io.div_result_rdy := io.ctrl.div_wb;
|
|
|
|
|
2011-11-02 01:59:27 +01:00
|
|
|
io.ctrl.div_rdy := div.io.div_rdy;
|
|
|
|
io.ctrl.div_result_val := div.io.div_result_val;
|
2011-10-26 08:02:47 +02:00
|
|
|
|
|
|
|
// multiplier
|
2012-01-03 00:42:39 +01:00
|
|
|
mul.io.mul_val := ex_reg_ctrl_mul_val;
|
|
|
|
mul.io.mul_kill:= mem_reg_ctrl_mul_val && io.ctrl.killm;
|
2011-12-17 16:20:00 +01:00
|
|
|
mul.io.dw := ex_reg_ctrl_fn_dw;
|
2011-10-26 08:02:47 +02:00
|
|
|
mul.io.mul_fn := ex_reg_ctrl_mul_fn;
|
|
|
|
mul.io.mul_tag := ex_reg_waddr;
|
|
|
|
mul.io.in0 := ex_reg_rs1;
|
|
|
|
mul.io.in1 := ex_reg_rs2;
|
2011-12-17 16:30:47 +01:00
|
|
|
|
|
|
|
io.ctrl.mul_rdy := mul.io.mul_rdy
|
2011-11-02 01:59:27 +01:00
|
|
|
io.ctrl.mul_result_val := mul.io.result_val;
|
2011-12-20 12:49:07 +01:00
|
|
|
mul.io.result_rdy := io.ctrl.mul_wb
|
2011-11-02 01:59:27 +01:00
|
|
|
|
2011-11-18 08:50:45 +01:00
|
|
|
io.ctrl.ex_waddr := ex_reg_waddr; // for load/use hazard detection & bypass control
|
2011-10-26 08:02:47 +02:00
|
|
|
|
2011-11-02 01:59:27 +01:00
|
|
|
// D$ request interface (registered inside D$ module)
|
|
|
|
// other signals (req_val, req_rdy) connect to control module
|
2012-01-24 09:15:17 +01:00
|
|
|
io.dmem.req_addr := ex_jr_target_extended.toUFix;
|
2012-02-08 08:54:25 +01:00
|
|
|
if (HAVE_FPU) {
|
|
|
|
io.dmem.req_data := Mux(io.ctrl.ex_fp_val, io.fpu.store_data, ex_reg_rs2)
|
|
|
|
io.dmem.req_tag := Cat(ex_reg_waddr, io.ctrl.ex_fp_val).toUFix
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
io.dmem.req_data := ex_reg_rs2
|
|
|
|
io.dmem.req_tag := Cat(ex_reg_waddr, Bool(false)).toUFix
|
|
|
|
}
|
2011-10-26 08:02:47 +02:00
|
|
|
|
2011-11-02 01:59:27 +01:00
|
|
|
// processor control regfile read
|
2011-11-10 09:50:09 +01:00
|
|
|
pcr.io.r.en := ex_reg_ctrl_ren_pcr | ex_reg_ctrl_eret;
|
2011-10-26 08:02:47 +02:00
|
|
|
pcr.io.r.addr :=
|
|
|
|
Mux(ex_reg_ctrl_eret, PCR_EPC,
|
2011-11-10 09:50:09 +01:00
|
|
|
ex_reg_raddr2);
|
|
|
|
|
2012-01-23 18:51:35 +01:00
|
|
|
pcr.io.host.from_wen <> io.host.from_wen;
|
|
|
|
pcr.io.host.from <> io.host.from;
|
|
|
|
pcr.io.host.to <> io.host.to;
|
2011-11-14 12:24:02 +01:00
|
|
|
|
|
|
|
io.ctrl.irq_timer := pcr.io.irq_timer;
|
|
|
|
io.ctrl.irq_ipi := pcr.io.irq_ipi;
|
2011-11-09 23:52:17 +01:00
|
|
|
io.ctrl.status := pcr.io.status;
|
|
|
|
io.ptbr := pcr.io.ptbr;
|
2011-11-14 13:13:13 +01:00
|
|
|
io.ptbr_wen := pcr.io.ptbr_wen;
|
2011-10-26 08:02:47 +02:00
|
|
|
io.debug.error_mode := pcr.io.debug.error_mode;
|
2011-11-02 01:59:27 +01:00
|
|
|
|
2011-10-26 08:02:47 +02:00
|
|
|
// branch resolution logic
|
2011-11-02 01:59:27 +01:00
|
|
|
io.ctrl.br_eq := (ex_reg_rs1 === ex_reg_rs2);
|
|
|
|
io.ctrl.br_ltu := (ex_reg_rs1.toUFix < ex_reg_rs2.toUFix);
|
|
|
|
io.ctrl.br_lt :=
|
|
|
|
(~(ex_reg_rs1(63) ^ ex_reg_rs2(63)) & io.ctrl.br_ltu |
|
2011-10-26 08:02:47 +02:00
|
|
|
ex_reg_rs1(63) & ~ex_reg_rs2(63)).toBool;
|
|
|
|
|
2011-11-16 11:04:28 +01:00
|
|
|
// time stamp counter
|
|
|
|
val tsc_reg = Reg(resetVal = UFix(0,64));
|
|
|
|
tsc_reg <== tsc_reg + UFix(1);
|
2012-01-02 06:28:38 +01:00
|
|
|
// instructions retired counter
|
|
|
|
val irt_reg = Reg(resetVal = UFix(0,64));
|
2012-01-18 06:12:31 +01:00
|
|
|
when (wb_reg_valid) { irt_reg <== irt_reg + UFix(1); }
|
2011-11-16 11:04:28 +01:00
|
|
|
|
2011-10-26 08:02:47 +02:00
|
|
|
// writeback select mux
|
|
|
|
ex_wdata :=
|
2011-11-02 01:59:27 +01:00
|
|
|
Mux(ex_reg_ctrl_ll_wb || ex_reg_ctrl_wen_pcr, ex_reg_rs1,
|
2012-02-02 22:33:27 +01:00
|
|
|
Mux(ex_reg_ctrl_sel_wb === WB_PC, Cat(Fill(64-VADDR_BITS, ex_pc_plus4(VADDR_BITS-1)), ex_pc_plus4),
|
2011-10-26 08:02:47 +02:00
|
|
|
Mux(ex_reg_ctrl_sel_wb === WB_PCR, ex_pcr,
|
2011-11-16 11:04:28 +01:00
|
|
|
Mux(ex_reg_ctrl_sel_wb === WB_TSC, tsc_reg,
|
2012-01-02 06:28:38 +01:00
|
|
|
Mux(ex_reg_ctrl_sel_wb === WB_IRT, irt_reg,
|
|
|
|
ex_alu_out))))).toBits; // WB_ALU
|
2011-10-26 08:02:47 +02:00
|
|
|
|
2011-11-02 01:59:27 +01:00
|
|
|
// memory stage
|
|
|
|
mem_reg_pc <== ex_reg_pc;
|
|
|
|
mem_reg_waddr <== ex_reg_waddr;
|
|
|
|
mem_reg_wdata <== ex_wdata;
|
|
|
|
mem_reg_ctrl_ll_wb <== ex_reg_ctrl_ll_wb;
|
|
|
|
mem_reg_raddr2 <== ex_reg_raddr2;
|
2012-01-03 00:42:39 +01:00
|
|
|
mem_reg_ctrl_mul_val <== ex_reg_ctrl_mul_val;
|
|
|
|
mem_reg_ctrl_div_val <== ex_reg_ctrl_div_val;
|
2011-11-18 08:50:45 +01:00
|
|
|
|
2011-11-02 01:59:27 +01:00
|
|
|
when (io.ctrl.killx) {
|
2011-11-04 23:40:41 +01:00
|
|
|
mem_reg_valid <== Bool(false);
|
2011-11-02 01:59:27 +01:00
|
|
|
mem_reg_ctrl_wen_pcr <== Bool(false);
|
|
|
|
}
|
|
|
|
otherwise {
|
2011-11-04 23:40:41 +01:00
|
|
|
mem_reg_valid <== ex_reg_valid;
|
2011-11-02 01:59:27 +01:00
|
|
|
mem_reg_ctrl_wen_pcr <== ex_reg_ctrl_wen_pcr;
|
|
|
|
}
|
|
|
|
|
2011-11-02 05:25:52 +01:00
|
|
|
// for load/use hazard detection (load byte/halfword)
|
|
|
|
io.ctrl.mem_waddr := mem_reg_waddr;
|
2011-11-14 12:24:02 +01:00
|
|
|
io.ctrl.mem_valid := mem_reg_valid;
|
2011-11-02 05:25:52 +01:00
|
|
|
|
2012-02-07 02:26:45 +01:00
|
|
|
mem_wdata := Mux(io.ctrl.mem_load, io.dmem.resp_data, mem_reg_wdata)
|
|
|
|
|
2011-11-02 21:32:32 +01:00
|
|
|
// 32/64 bit load handling (moved to earlier in file)
|
2011-11-02 05:25:52 +01:00
|
|
|
|
2011-11-02 01:59:27 +01:00
|
|
|
// writeback stage
|
2012-02-08 08:54:25 +01:00
|
|
|
val dmem_resp_fpu = if (HAVE_FPU) io.dmem.resp_tag(0).toBool else Bool(false)
|
|
|
|
r_dmem_resp_replay <== io.dmem.resp_replay && !dmem_resp_fpu;
|
|
|
|
r_dmem_fp_replay <== io.dmem.resp_replay && dmem_resp_fpu;
|
|
|
|
r_dmem_resp_waddr <== io.dmem.resp_tag.toUFix >> UFix(1)
|
2011-11-02 01:59:27 +01:00
|
|
|
|
2012-01-03 00:42:39 +01:00
|
|
|
wb_reg_pc <== mem_reg_pc;
|
2011-11-02 21:32:32 +01:00
|
|
|
wb_reg_waddr <== mem_reg_waddr;
|
|
|
|
wb_reg_wdata <== mem_reg_wdata;
|
|
|
|
wb_reg_ctrl_ll_wb <== mem_reg_ctrl_ll_wb;
|
2012-01-03 00:42:39 +01:00
|
|
|
wb_reg_raddr2 <== mem_reg_raddr2;
|
2011-11-02 01:59:27 +01:00
|
|
|
|
|
|
|
when (io.ctrl.killm) {
|
2012-01-18 06:12:31 +01:00
|
|
|
wb_reg_valid <== Bool(false);
|
2012-01-03 00:42:39 +01:00
|
|
|
wb_reg_ctrl_wen_pcr <== Bool(false);
|
2011-11-02 01:59:27 +01:00
|
|
|
}
|
|
|
|
otherwise {
|
2012-01-18 06:12:31 +01:00
|
|
|
wb_reg_valid <== mem_reg_valid;
|
2012-01-03 00:42:39 +01:00
|
|
|
wb_reg_ctrl_wen_pcr <== mem_reg_ctrl_wen_pcr;
|
2011-11-02 01:59:27 +01:00
|
|
|
}
|
|
|
|
|
2011-10-26 08:02:47 +02:00
|
|
|
// regfile write
|
2012-02-02 00:36:01 +01:00
|
|
|
wb_wdata := Mux(Reg(io.ctrl.mem_load), io.dmem.resp_data_subword, wb_reg_wdata)
|
2011-11-02 01:59:27 +01:00
|
|
|
rfile.io.w0.addr := wb_reg_waddr;
|
2012-02-08 08:54:25 +01:00
|
|
|
rfile.io.w0.en := io.ctrl.wb_wen || wb_reg_ctrl_ll_wb;
|
2012-02-02 00:36:01 +01:00
|
|
|
rfile.io.w0.data := wb_wdata
|
2011-10-26 08:02:47 +02:00
|
|
|
|
2011-11-02 07:14:34 +01:00
|
|
|
io.ctrl.wb_waddr := wb_reg_waddr;
|
2012-02-08 08:54:25 +01:00
|
|
|
io.ctrl.mem_wb := r_dmem_resp_replay;
|
2011-10-26 08:02:47 +02:00
|
|
|
|
2011-11-02 01:59:27 +01:00
|
|
|
// scoreboard clear (for div/mul and D$ load miss writebacks)
|
2012-01-02 11:51:30 +01:00
|
|
|
io.ctrl.sboard_clr := id_ctrl_ll_wb;
|
|
|
|
io.ctrl.sboard_clra := id_waddr;
|
2012-02-08 08:54:25 +01:00
|
|
|
io.ctrl.fp_sboard_clr := r_dmem_fp_replay;
|
|
|
|
io.ctrl.fp_sboard_clra := r_dmem_resp_waddr;
|
2011-11-02 01:59:27 +01:00
|
|
|
|
|
|
|
// processor control regfile write
|
2012-01-03 00:42:39 +01:00
|
|
|
pcr.io.w.addr := wb_reg_raddr2;
|
|
|
|
pcr.io.w.en := wb_reg_ctrl_wen_pcr;
|
|
|
|
pcr.io.w.data := wb_reg_wdata;
|
2011-10-26 08:02:47 +02:00
|
|
|
|
2011-11-14 22:48:49 +01:00
|
|
|
pcr.io.di := io.ctrl.irq_disable;
|
|
|
|
pcr.io.ei := io.ctrl.irq_enable;
|
2012-01-03 00:42:39 +01:00
|
|
|
pcr.io.eret := io.ctrl.wb_eret;
|
2011-11-18 08:50:45 +01:00
|
|
|
pcr.io.exception := io.ctrl.exception;
|
|
|
|
pcr.io.cause := io.ctrl.cause;
|
2012-01-03 00:42:39 +01:00
|
|
|
pcr.io.pc := wb_reg_pc;
|
2011-11-18 08:50:45 +01:00
|
|
|
pcr.io.badvaddr_wen := io.ctrl.badvaddr_wen;
|
2011-12-01 07:51:59 +01:00
|
|
|
io.console.bits := pcr.io.console_data;
|
|
|
|
io.console.valid := pcr.io.console_val;
|
2011-10-26 08:02:47 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
}
|