Refactored coherence as member rather than trait. MI and MEI protocols.
This commit is contained in:
Henry Cook
parent
e71e3ce38f
commit
b22d7f8192
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@ -50,7 +50,7 @@ object cpuCmdToRW {
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}
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}
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trait CoherencePolicy {
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abstract class CoherencePolicy {
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def isHit (cmd: Bits, state: UFix): Bool
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def isValid (state: UFix): Bool
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@ -72,9 +72,10 @@ trait CoherencePolicy {
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def newProbeReply (incoming: ProbeRequest, state: UFix): ProbeReply
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def hasData (reply: ProbeReply): Bool
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def hasData (init: TransactionInit): Bool
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def hasData (reply: TransactionReply): Bool
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def messageHasData (reply: ProbeReply): Bool
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def messageHasData (init: TransactionInit): Bool
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def messageHasData (reply: TransactionReply): Bool
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def messageUpdatesDataArray (reply: TransactionReply): Bool
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def isCoherenceConflict(addr1: Bits, addr2: Bits): Bool
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def getTransactionReplyType(x_type: UFix, count: UFix): Bits
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@ -84,7 +85,14 @@ trait CoherencePolicy {
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def needsAckReply(x_type: UFix, global_state: UFix): Bool
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}
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trait IncoherentPolicy extends CoherencePolicy {
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trait UncachedTransactions {
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def getTransactionInitTypeOnUncachedRead(): UFix
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def getTransactionInitTypeOnUncachedWrite(): UFix
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}
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abstract class CoherencePolicyWithUncached extends CoherencePolicy with UncachedTransactions
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abstract class IncoherentPolicy extends CoherencePolicy {
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// UNIMPLEMENTED
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def newStateOnProbeRequest(incoming: ProbeRequest, state: UFix): Bits = state
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def newProbeReply (incoming: ProbeRequest, state: UFix): ProbeReply = {
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@ -93,7 +101,7 @@ trait IncoherentPolicy extends CoherencePolicy {
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reply.global_xact_id := UFix(0)
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reply
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}
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def hasData (reply: ProbeReply) = Bool(false)
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def messageHasData (reply: ProbeReply) = Bool(false)
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def isCoherenceConflict(addr1: Bits, addr2: Bits): Bool = Bool(false)
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def getTransactionReplyType(x_type: UFix, count: UFix): Bits = Bits(0)
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def getProbeRequestType(x_type: UFix, global_state: UFix): UFix = UFix(0)
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@ -102,7 +110,7 @@ trait IncoherentPolicy extends CoherencePolicy {
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def needsAckReply(x_type: UFix, global_state: UFix): Bool = Bool(false)
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}
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trait ThreeStateIncoherence extends IncoherentPolicy {
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class ThreeStateIncoherence extends IncoherentPolicy {
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val tileInvalid :: tileClean :: tileDirty :: Nil = Enum(3){ UFix() }
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val xactInitReadClean :: xactInitReadDirty :: xactInitWriteback :: Nil = Enum(3){ UFix() }
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val xactReplyData :: xactReplyAck :: Nil = Enum(2){ UFix() }
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@ -141,11 +149,256 @@ trait ThreeStateIncoherence extends IncoherentPolicy {
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def getTransactionInitTypeOnCacheControl(cmd: Bits): Bits = xactInitWriteback //TODO
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def getTransactionInitTypeOnWriteback(): Bits = xactInitWriteback
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def hasData (init: TransactionInit): Bool = (init.x_type === xactInitWriteback)
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def hasData (reply: TransactionReply) = (reply.x_type === xactReplyData)
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def messageHasData (init: TransactionInit): Bool = (init.x_type === xactInitWriteback)
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def messageHasData (reply: TransactionReply) = (reply.x_type === xactReplyData)
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def messageUpdatesDataArray (reply: TransactionReply) = (reply.x_type === xactReplyData)
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}
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trait FourStateCoherence extends CoherencePolicy {
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class TwoStateCoherence extends CoherencePolicyWithUncached {
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val tileInvalid :: tileValid :: Nil = Enum(2){ UFix() }
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val globalInvalid :: globalValid :: Nil = Enum(2){ UFix() }
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val xactInitReadExclusive :: xactInitReadUncached :: xactInitWriteUncached :: Nil = Enum(3){ UFix() }
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val xactReplyReadExclusive :: xactReplyReadUncached :: xactReplyWriteUncached :: Nil = Enum(3){ UFix() }
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val probeReqInvalidate :: probeReqCopy :: Nil = Enum(2){ UFix() }
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val probeRepInvalidateData :: probeRepCopyData :: probeRepInvalidateAck :: probeRepCopyAck :: Nil = Enum(4){ UFix() }
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def isHit (cmd: Bits, state: UFix): Bool = state != tileInvalid
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def isValid (state: UFix): Bool = state != tileInvalid
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def needsTransactionOnSecondaryMiss(cmd: Bits, outstanding: TransactionInit): Bool = (outstanding.x_type != xactInitReadExclusive)
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def needsTransactionOnCacheControl(cmd: Bits, state: UFix): Bool = {
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MuxLookup(cmd, (state === tileValid), Array(
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M_INV -> (state === tileValid),
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M_CLN -> (state === tileValid)
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))
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}
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def needsWriteback (state: UFix): Bool = {
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needsTransactionOnCacheControl(M_INV, state)
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}
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def newStateOnHit(cmd: Bits, state: UFix): UFix = state
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def newStateOnCacheControl(cmd: Bits) = {
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MuxLookup(cmd, tileInvalid, Array(
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M_INV -> tileInvalid,
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M_CLN -> tileValid
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))
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}
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def newStateOnWriteback() = newStateOnCacheControl(M_INV)
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def newStateOnFlush() = newStateOnCacheControl(M_INV)
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def newStateOnTransactionReply(incoming: TransactionReply, outstanding: TransactionInit): UFix = {
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MuxLookup(incoming.x_type, tileInvalid, Array(
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xactReplyReadExclusive -> tileValid,
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xactReplyReadUncached -> tileInvalid,
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xactReplyWriteUncached -> tileInvalid
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))
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}
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def newStateOnProbeRequest(incoming: ProbeRequest, state: UFix): Bits = {
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MuxLookup(incoming.p_type, state, Array(
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probeReqInvalidate -> tileInvalid,
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probeReqCopy -> state
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))
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}
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def getTransactionInitTypeOnUncachedRead() = xactInitReadUncached
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def getTransactionInitTypeOnUncachedWrite() = xactInitWriteUncached
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def getTransactionInitTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix = xactInitReadExclusive
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def getTransactionInitTypeOnSecondaryMiss(cmd: Bits, state: UFix, outstanding: TransactionInit): UFix = xactInitReadExclusive
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def getTransactionInitTypeOnCacheControl(cmd: Bits): Bits = xactInitWriteUncached
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def getTransactionInitTypeOnWriteback(): Bits = getTransactionInitTypeOnCacheControl(M_INV)
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def newProbeReply (incoming: ProbeRequest, state: UFix): ProbeReply = {
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val reply = Wire() { new ProbeReply() }
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val with_data = MuxLookup(incoming.p_type, probeRepInvalidateData, Array(
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probeReqInvalidate -> probeRepInvalidateData,
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probeReqCopy -> probeRepCopyData
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))
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val without_data = MuxLookup(incoming.p_type, probeRepInvalidateAck, Array(
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probeReqInvalidate -> probeRepInvalidateAck,
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probeReqCopy -> probeRepCopyAck
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))
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reply.p_type := Mux(needsWriteback(state), with_data, without_data)
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reply.global_xact_id := incoming.global_xact_id
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reply
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}
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def messageHasData (reply: ProbeReply): Bool = {
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(reply.p_type === probeRepInvalidateData ||
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reply.p_type === probeRepCopyData)
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}
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def messageHasData (init: TransactionInit): Bool = {
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(init.x_type === xactInitWriteUncached)
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}
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def messageHasData (reply: TransactionReply): Bool = {
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(reply.x_type != xactReplyWriteUncached)
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}
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def messageUpdatesDataArray (reply: TransactionReply): Bool = {
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(reply.x_type === xactReplyReadExclusive)
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}
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def isCoherenceConflict(addr1: Bits, addr2: Bits): Bool = (addr1 === addr2)
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def getTransactionReplyType(x_type: UFix, count: UFix): Bits = {
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MuxLookup(x_type, xactReplyReadUncached, Array(
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xactInitReadExclusive -> xactReplyReadExclusive,
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xactInitReadUncached -> xactReplyReadUncached,
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xactInitWriteUncached -> xactReplyWriteUncached
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))
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}
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def getProbeRequestType(x_type: UFix, global_state: UFix): UFix = {
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MuxLookup(x_type, probeReqCopy, Array(
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xactInitReadExclusive -> probeReqInvalidate,
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xactInitReadUncached -> probeReqCopy,
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xactInitWriteUncached -> probeReqInvalidate
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))
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}
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def needsMemRead(x_type: UFix, global_state: UFix): Bool = {
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(x_type != xactInitWriteUncached)
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}
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def needsMemWrite(x_type: UFix, global_state: UFix): Bool = {
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(x_type === xactInitWriteUncached)
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}
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def needsAckReply(x_type: UFix, global_state: UFix): Bool = {
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(x_type === xactInitWriteUncached)
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}
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}
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class ThreeStateCoherence extends CoherencePolicyWithUncached { //MEI
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val tileInvalid :: tileExclusiveClean :: tileExclusiveDirty :: Nil = Enum(3){ UFix() }
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val globalInvalid :: globalExclusiveClean :: Nil = Enum(2){ UFix() }
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val xactInitReadExclusiveClean :: xactInitReadExclusiveDirty :: xactInitReadUncached :: xactInitWriteUncached :: Nil = Enum(4){ UFix() }
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val xactReplyReadExclusive :: xactReplyReadUncached :: xactReplyWriteUncached :: xactReplyReadExclusiveAck :: Nil = Enum(4){ UFix() }
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val probeReqInvalidate :: probeReqDowngrade :: probeReqCopy :: Nil = Enum(3){ UFix() }
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val probeRepInvalidateData :: probeRepDowngradeData :: probeRepCopyData :: probeRepInvalidateAck :: probeRepDowngradeAck :: probeRepCopyAck :: Nil = Enum(6){ UFix() }
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def isHit (cmd: Bits, state: UFix): Bool = state != tileInvalid
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def isValid (state: UFix): Bool = state != tileInvalid
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def needsTransactionOnSecondaryMiss(cmd: Bits, outstanding: TransactionInit): Bool = {
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val (read, write) = cpuCmdToRW(cmd)
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(read && (outstanding.x_type === xactInitReadUncached || outstanding.x_type === xactInitWriteUncached)) ||
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(write && (outstanding.x_type != xactInitReadExclusiveDirty))
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}
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def needsTransactionOnCacheControl(cmd: Bits, state: UFix): Bool = {
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MuxLookup(cmd, (state === tileExclusiveDirty), Array(
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M_INV -> (state === tileExclusiveDirty),
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M_CLN -> (state === tileExclusiveDirty)
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))
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}
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def needsWriteback (state: UFix): Bool = {
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needsTransactionOnCacheControl(M_INV, state)
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}
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def newStateOnHit(cmd: Bits, state: UFix): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, tileExclusiveDirty, state)
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}
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def newStateOnCacheControl(cmd: Bits) = {
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MuxLookup(cmd, tileInvalid, Array(
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M_INV -> tileInvalid,
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M_CLN -> tileExclusiveClean
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))
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}
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def newStateOnWriteback() = newStateOnCacheControl(M_INV)
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def newStateOnFlush() = newStateOnCacheControl(M_INV)
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def newStateOnTransactionReply(incoming: TransactionReply, outstanding: TransactionInit): UFix = {
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MuxLookup(incoming.x_type, tileInvalid, Array(
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xactReplyReadExclusive -> Mux(outstanding.x_type === xactInitReadExclusiveDirty, tileExclusiveDirty, tileExclusiveClean),
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xactReplyReadExclusiveAck -> tileExclusiveDirty,
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xactReplyReadUncached -> tileInvalid,
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xactReplyWriteUncached -> tileInvalid
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))
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}
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def newStateOnProbeRequest(incoming: ProbeRequest, state: UFix): Bits = {
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MuxLookup(incoming.p_type, state, Array(
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probeReqInvalidate -> tileInvalid,
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probeReqDowngrade -> tileExclusiveClean,
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probeReqCopy -> state
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))
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}
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def getTransactionInitTypeOnUncachedRead() = xactInitReadUncached
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def getTransactionInitTypeOnUncachedWrite() = xactInitWriteUncached
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def getTransactionInitTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, xactInitReadExclusiveDirty, xactInitReadExclusiveClean)
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}
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def getTransactionInitTypeOnSecondaryMiss(cmd: Bits, state: UFix, outstanding: TransactionInit): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, xactInitReadExclusiveDirty, outstanding.x_type)
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}
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def getTransactionInitTypeOnCacheControl(cmd: Bits): Bits = xactInitWriteUncached
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def getTransactionInitTypeOnWriteback(): Bits = getTransactionInitTypeOnCacheControl(M_INV)
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def newProbeReply (incoming: ProbeRequest, state: UFix): ProbeReply = {
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val reply = Wire() { new ProbeReply() }
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val with_data = MuxLookup(incoming.p_type, probeRepInvalidateData, Array(
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probeReqInvalidate -> probeRepInvalidateData,
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probeReqDowngrade -> probeRepDowngradeData,
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probeReqCopy -> probeRepCopyData
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))
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val without_data = MuxLookup(incoming.p_type, probeRepInvalidateAck, Array(
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probeReqInvalidate -> probeRepInvalidateAck,
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probeReqDowngrade -> probeRepDowngradeAck,
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probeReqCopy -> probeRepCopyAck
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))
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reply.p_type := Mux(needsWriteback(state), with_data, without_data)
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reply.global_xact_id := incoming.global_xact_id
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reply
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}
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def messageHasData (reply: ProbeReply): Bool = {
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(reply.p_type === probeRepInvalidateData ||
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reply.p_type === probeRepDowngradeData ||
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reply.p_type === probeRepCopyData)
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}
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def messageHasData (init: TransactionInit): Bool = {
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(init.x_type === xactInitWriteUncached)
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}
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def messageHasData (reply: TransactionReply): Bool = {
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(reply.x_type != xactReplyWriteUncached && reply.x_type != xactReplyReadExclusiveAck)
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}
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def messageUpdatesDataArray (reply: TransactionReply): Bool = {
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(reply.x_type === xactReplyReadExclusive)
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}
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def isCoherenceConflict(addr1: Bits, addr2: Bits): Bool = (addr1 === addr2)
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def getTransactionReplyType(x_type: UFix, count: UFix): Bits = {
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MuxLookup(x_type, xactReplyReadUncached, Array(
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xactInitReadExclusiveClean -> xactReplyReadExclusive,
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xactInitReadExclusiveDirty -> xactReplyReadExclusive,
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xactInitReadUncached -> xactReplyReadUncached,
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xactInitWriteUncached -> xactReplyWriteUncached
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))
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}
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def getProbeRequestType(x_type: UFix, global_state: UFix): UFix = {
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MuxLookup(x_type, probeReqCopy, Array(
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xactInitReadExclusiveClean -> probeReqInvalidate,
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xactInitReadExclusiveDirty -> probeReqInvalidate,
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xactInitReadUncached -> probeReqCopy,
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xactInitWriteUncached -> probeReqInvalidate
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))
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}
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def needsMemRead(x_type: UFix, global_state: UFix): Bool = {
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(x_type != xactInitWriteUncached)
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}
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def needsMemWrite(x_type: UFix, global_state: UFix): Bool = {
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(x_type === xactInitWriteUncached)
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}
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def needsAckReply(x_type: UFix, global_state: UFix): Bool = {
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(x_type === xactInitWriteUncached)
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}
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}
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class FourStateCoherence extends CoherencePolicyWithUncached {
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val tileInvalid :: tileShared :: tileExclusiveClean :: tileExclusiveDirty :: Nil = Enum(4){ UFix() }
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val globalInvalid :: globalShared :: globalExclusiveClean :: Nil = Enum(3){ UFix() }
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@ -208,6 +461,8 @@ trait FourStateCoherence extends CoherencePolicy {
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))
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}
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def getTransactionInitTypeOnUncachedRead() = xactInitReadUncached
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def getTransactionInitTypeOnUncachedWrite() = xactInitWriteUncached
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def getTransactionInitTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write || cmd === M_PFW, xactInitReadExclusive, xactInitReadShared)
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@ -236,17 +491,20 @@ trait FourStateCoherence extends CoherencePolicy {
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reply
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}
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def hasData (reply: ProbeReply): Bool = {
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def messageHasData (reply: ProbeReply): Bool = {
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(reply.p_type === probeRepInvalidateData ||
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reply.p_type === probeRepDowngradeData ||
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reply.p_type === probeRepCopyData)
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}
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def hasData (init: TransactionInit): Bool = {
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def messageHasData (init: TransactionInit): Bool = {
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(init.x_type === xactInitWriteUncached)
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}
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def hasData (reply: TransactionReply): Bool = {
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def messageHasData (reply: TransactionReply): Bool = {
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(reply.x_type != xactReplyWriteUncached && reply.x_type != xactReplyReadExclusiveAck)
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}
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def messageUpdatesDataArray (reply: TransactionReply): Bool = {
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(reply.x_type === xactReplyReadShared || reply.x_type === xactReplyReadExclusive)
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}
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def isCoherenceConflict(addr1: Bits, addr2: Bits): Bool = (addr1 === addr2)
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@ -50,7 +50,7 @@ class ioTileLink extends Bundle {
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val xact_finish = (new ioDecoupled) { new TransactionFinish }
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}
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class XactTracker(ntiles: Int, id: Int) extends Component with FourStateCoherence {
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class XactTracker(ntiles: Int, id: Int, co: CoherencePolicy) extends Component {
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val io = new Bundle {
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val alloc_req = (new ioDecoupled) { new TrackerAllocReq }.flip
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val p_data = (new ioPipe) { new TrackerProbeData }.flip
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@ -140,7 +140,7 @@ class XactTracker(ntiles: Int, id: Int) extends Component with FourStateCoherenc
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io.sharer_count := UFix(ntiles) // TODO: Broadcast only
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io.x_type := x_type_
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io.mem_req_cmd.valid := Bool(false)
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io.mem_req_cmd.valid := Bool(false)
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io.mem_req_cmd.bits.rw := Bool(false)
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io.mem_req_cmd.bits.addr := addr_
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io.mem_req_cmd.bits.tag := UFix(id)
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@ -148,7 +148,7 @@ class XactTracker(ntiles: Int, id: Int) extends Component with FourStateCoherenc
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io.mem_req_data.bits.data := UFix(0)
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io.mem_req_lock := Bool(false)
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io.probe_req.valid := Bool(false)
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io.probe_req.bits.p_type := getProbeRequestType(x_type_, UFix(0))
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io.probe_req.bits.p_type := co.getProbeRequestType(x_type_, UFix(0))
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io.probe_req.bits.global_xact_id := UFix(id)
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io.probe_req.bits.address := addr_
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io.push_p_req := Bits(0, width = ntiles)
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@ -167,8 +167,8 @@ class XactTracker(ntiles: Int, id: Int) extends Component with FourStateCoherenc
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x_type_ := io.alloc_req.bits.xact_init.x_type
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init_tile_id_ := io.alloc_req.bits.tile_id
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tile_xact_id_ := io.alloc_req.bits.xact_init.tile_xact_id
|
||||
x_init_data_needs_write := hasData(io.alloc_req.bits.xact_init)
|
||||
x_needs_read := needsMemRead(io.alloc_req.bits.xact_init.x_type, UFix(0))
|
||||
x_init_data_needs_write := co.messageHasData(io.alloc_req.bits.xact_init)
|
||||
x_needs_read := co.needsMemRead(io.alloc_req.bits.xact_init.x_type, UFix(0))
|
||||
if(ntiles > 1) p_rep_count := UFix(ntiles-1)
|
||||
val p_req_initial_flags = ~( UFix(1) << io.alloc_req.bits.tile_id ) //TODO: Broadcast only
|
||||
p_req_flags := p_req_initial_flags
|
||||
|
|
@ -226,7 +226,7 @@ class XactTracker(ntiles: Int, id: Int) extends Component with FourStateCoherenc
|
|||
} . elsewhen (x_needs_read) {
|
||||
doMemReqRead(io.mem_req_cmd, x_needs_read)
|
||||
} . otherwise {
|
||||
state := Mux(needsAckReply(x_type_, UFix(0)), s_ack, s_busy)
|
||||
state := Mux(co.needsAckReply(x_type_, UFix(0)), s_ack, s_busy)
|
||||
}
|
||||
}
|
||||
is(s_ack) {
|
||||
|
|
@ -241,17 +241,17 @@ class XactTracker(ntiles: Int, id: Int) extends Component with FourStateCoherenc
|
|||
}
|
||||
}
|
||||
|
||||
abstract class CoherenceHub(ntiles: Int) extends Component with CoherencePolicy {
|
||||
abstract class CoherenceHub(ntiles: Int, co: CoherencePolicy) extends Component {
|
||||
val io = new Bundle {
|
||||
val tiles = Vec(ntiles) { new ioTileLink() }.flip
|
||||
val mem = new ioMem
|
||||
}
|
||||
}
|
||||
|
||||
class CoherenceHubNull extends CoherenceHub(1) with ThreeStateIncoherence
|
||||
class CoherenceHubNull(co: ThreeStateIncoherence) extends CoherenceHub(1, co)
|
||||
{
|
||||
val x_init = io.tiles(0).xact_init
|
||||
val is_write = x_init.bits.x_type === xactInitWriteback
|
||||
val is_write = x_init.bits.x_type === co.xactInitWriteback
|
||||
x_init.ready := io.mem.req_cmd.ready && !(is_write && io.mem.resp.valid) //stall write req/resp to handle previous read resp
|
||||
io.mem.req_cmd.valid := x_init.valid && !(is_write && io.mem.resp.valid)
|
||||
io.mem.req_cmd.bits.rw := is_write
|
||||
|
|
@ -260,7 +260,7 @@ class CoherenceHubNull extends CoherenceHub(1) with ThreeStateIncoherence
|
|||
io.mem.req_data <> io.tiles(0).xact_init_data
|
||||
|
||||
val x_rep = io.tiles(0).xact_rep
|
||||
x_rep.bits.x_type := Mux(io.mem.resp.valid, xactReplyData, xactReplyAck)
|
||||
x_rep.bits.x_type := Mux(io.mem.resp.valid, co.xactReplyData, co.xactReplyAck)
|
||||
x_rep.bits.tile_xact_id := Mux(io.mem.resp.valid, io.mem.resp.bits.tag, x_init.bits.tile_xact_id)
|
||||
x_rep.bits.global_xact_id := UFix(0) // don't care
|
||||
x_rep.bits.data := io.mem.resp.bits.data
|
||||
|
|
@ -275,9 +275,9 @@ class CoherenceHubNull extends CoherenceHub(1) with ThreeStateIncoherence
|
|||
}
|
||||
|
||||
|
||||
class CoherenceHubBroadcast(ntiles: Int) extends CoherenceHub(ntiles) with FourStateCoherence
|
||||
class CoherenceHubBroadcast(ntiles: Int, co: CoherencePolicy) extends CoherenceHub(ntiles, co)
|
||||
{
|
||||
val trackerList = (0 until NGLOBAL_XACTS).map(new XactTracker(ntiles, _))
|
||||
val trackerList = (0 until NGLOBAL_XACTS).map(new XactTracker(ntiles, _, co))
|
||||
|
||||
val busy_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} }
|
||||
val addr_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=PADDR_BITS-OFFSET_BITS)} }
|
||||
|
|
@ -344,12 +344,12 @@ class CoherenceHubBroadcast(ntiles: Int) extends CoherenceHub(ntiles) with FourS
|
|||
rep.bits.require_ack := Bool(true)
|
||||
rep.valid := Bool(false)
|
||||
when(io.mem.resp.valid && (UFix(j) === init_tile_id_arr(mem_idx))) {
|
||||
rep.bits.x_type := getTransactionReplyType(x_type_arr(mem_idx), sh_count_arr(mem_idx))
|
||||
rep.bits.x_type := co.getTransactionReplyType(x_type_arr(mem_idx), sh_count_arr(mem_idx))
|
||||
rep.bits.tile_xact_id := tile_xact_id_arr(mem_idx)
|
||||
rep.bits.global_xact_id := mem_idx
|
||||
rep.valid := Bool(true)
|
||||
} . otherwise {
|
||||
rep.bits.x_type := getTransactionReplyType(x_type_arr(ack_idx), sh_count_arr(ack_idx))
|
||||
rep.bits.x_type := co.getTransactionReplyType(x_type_arr(ack_idx), sh_count_arr(ack_idx))
|
||||
rep.bits.tile_xact_id := tile_xact_id_arr(ack_idx)
|
||||
rep.bits.global_xact_id := ack_idx
|
||||
when (UFix(j) === init_tile_id_arr(ack_idx)) {
|
||||
|
|
@ -417,16 +417,16 @@ class CoherenceHubBroadcast(ntiles: Int) extends CoherenceHub(ntiles) with FourS
|
|||
val conflicts = Vec(NGLOBAL_XACTS) { Wire() { Bool() } }
|
||||
for( i <- 0 until NGLOBAL_XACTS) {
|
||||
val t = trackerList(i).io
|
||||
conflicts(i) := t.busy && x_init.valid && isCoherenceConflict(t.addr, x_init.bits.address)
|
||||
conflicts(i) := t.busy && x_init.valid && co.isCoherenceConflict(t.addr, x_init.bits.address)
|
||||
}
|
||||
x_abort.bits.tile_xact_id := x_init.bits.tile_xact_id
|
||||
want_to_abort_arr(j) := x_init.valid && (conflicts.toBits.orR || busy_arr.toBits.andR || (!x_init_data_dep_list(j).io.enq.ready && hasData(x_init.bits)))
|
||||
want_to_abort_arr(j) := x_init.valid && (conflicts.toBits.orR || busy_arr.toBits.andR || (!x_init_data_dep_list(j).io.enq.ready && co.messageHasData(x_init.bits)))
|
||||
|
||||
x_abort.valid := Bool(false)
|
||||
switch(abort_state_arr(j)) {
|
||||
is(s_idle) {
|
||||
when(want_to_abort_arr(j)) {
|
||||
when(hasData(x_init.bits)) {
|
||||
when(co.messageHasData(x_init.bits)) {
|
||||
abort_state_arr(j) := s_abort_drain
|
||||
} . otherwise {
|
||||
abort_state_arr(j) := s_abort_send
|
||||
|
|
@ -478,7 +478,7 @@ class CoherenceHubBroadcast(ntiles: Int) extends CoherenceHub(ntiles) with FourS
|
|||
init_arb.io.in(j).bits.tile_id := UFix(j)
|
||||
val pop_x_inits = trackerList.map(_.io.pop_x_init(j).toBool)
|
||||
val do_pop = foldR(pop_x_inits)(_||_)
|
||||
x_init_data_dep_list(j).io.enq.valid := do_pop && hasData(x_init.bits) && (abort_state_arr(j) === s_idle)
|
||||
x_init_data_dep_list(j).io.enq.valid := do_pop && co.messageHasData(x_init.bits) && (abort_state_arr(j) === s_idle)
|
||||
x_init_data_dep_list(j).io.enq.bits.global_xact_id := OHToUFix(pop_x_inits)
|
||||
x_init.ready := (abort_state_arr(j) === s_abort_complete) || do_pop
|
||||
x_init_data.ready := (abort_state_arr(j) === s_abort_drain) || foldR(trackerList.map(_.io.pop_x_init_data(j).toBool))(_||_)
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user