2014-09-12 19:15:04 +02:00
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// See LICENSE for license details.
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2014-09-01 05:26:55 +02:00
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package rocketchip
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2012-10-09 22:05:56 +02:00
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import Chisel._
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import uncore._
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import rocket._
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2013-01-25 08:56:45 +01:00
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import rocket.Util._
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2012-10-09 22:05:56 +02:00
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2014-08-08 21:27:47 +02:00
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case object NTiles extends Field[Int]
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case object NBanks extends Field[Int]
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case object BankIdLSB extends Field[Int]
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2014-08-23 10:26:03 +02:00
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case object CacheBlockBytes extends Field[Int]
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case object CacheBlockOffsetBits extends Field[Int]
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2014-08-25 04:30:53 +02:00
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case object BuildDRAMSideLLC extends Field[(Int) => DRAMSideLLCLike]
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case object BuildCoherenceMaster extends Field[(Int) => CoherenceAgent]
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case object UseBackupMemoryPort extends Field[Boolean]
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2014-08-08 21:27:47 +02:00
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case object Coherence extends Field[CoherencePolicyWithUncached]
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2013-08-24 22:20:38 +02:00
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2014-08-25 04:30:53 +02:00
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abstract trait TopLevelParameters extends UsesParameters {
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val htifW = params(HTIFWidth)
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val nTiles = params(NTiles)
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val nBanks = params(NBanks)
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val lsb = params(BankIdLSB)
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val refillCycles = params(MIFDataBeats)
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}
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class OuterMemorySystem extends Module with TopLevelParameters {
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2012-10-09 22:05:56 +02:00
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val io = new Bundle {
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2014-08-08 21:27:47 +02:00
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val tiles = Vec.fill(params(NTiles)){new TileLinkIO}.flip
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2013-01-07 23:19:55 +01:00
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val htif = (new TileLinkIO).flip
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2014-08-08 21:27:47 +02:00
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val incoherent = Vec.fill(params(LNClients)){Bool()}.asInput
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2014-03-30 17:13:05 +02:00
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val mem = new MemIO
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2014-08-08 21:27:47 +02:00
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val mem_backup = new MemSerializedIO(params(HTIFWidth))
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2012-10-09 22:05:56 +02:00
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val mem_backup_en = Bool(INPUT)
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}
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2014-08-25 04:30:53 +02:00
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// Create a simple NoC and points of coherence serialization
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2014-09-01 05:26:55 +02:00
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val net = Module(new RocketChipCrossbarNetwork)
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2014-08-25 04:30:53 +02:00
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val masterEndpoints = (0 until params(NBanks)).map(params(BuildCoherenceMaster))
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2014-01-21 21:37:47 +01:00
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net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end }
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2014-04-30 01:50:07 +02:00
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net.io.masters zip (masterEndpoints.map(_.io.inner)) map { case (net, end) => net <> end }
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2013-08-03 00:02:09 +02:00
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masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } }
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2013-03-20 22:11:54 +01:00
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2014-08-25 04:30:53 +02:00
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// Create a converter between TileLinkIO and MemIO
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2014-09-24 20:34:16 +02:00
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val conv = Module(new MemIOUncachedTileLinkIOConverter(2),
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{ case TLId => "outer" })
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2014-08-08 21:27:47 +02:00
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if(params(NBanks) > 1) {
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2014-09-24 20:34:16 +02:00
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val arb = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(params(NBanks)),
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{ case TLId => "outer" })
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2014-04-30 01:50:07 +02:00
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arb.io.in zip masterEndpoints.map(_.io.outer) map { case (arb, cache) => arb <> cache }
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2013-03-20 22:11:54 +01:00
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conv.io.uncached <> arb.io.out
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} else {
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2014-04-30 01:50:07 +02:00
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conv.io.uncached <> masterEndpoints.head.io.outer
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2012-10-09 22:05:56 +02:00
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}
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2014-08-25 04:30:53 +02:00
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// Create a DRAM-side LLC
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val llc = params(BuildDRAMSideLLC)(refillCycles)
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llc.io.cpu.req_cmd <> Queue(conv.io.mem.req_cmd, 2)
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llc.io.cpu.req_data <> Queue(conv.io.mem.req_data, refillCycles)
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conv.io.mem.resp <> llc.io.cpu.resp
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// Create a SerDes for backup memory port
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if(params(UseBackupMemoryPort)) {
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VLSIUtils.doOuterMemorySystemSerdes(llc.io.mem, io.mem, io.mem_backup,
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2014-08-28 22:07:54 +02:00
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io.mem_backup_en, htifW)
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2014-08-25 04:30:53 +02:00
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} else {
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io.mem <> llc.io.mem
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}
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2012-10-09 22:05:56 +02:00
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}
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2014-08-25 04:30:53 +02:00
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class Uncore extends Module with TopLevelParameters {
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2012-10-09 22:05:56 +02:00
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val io = new Bundle {
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2014-08-25 04:30:53 +02:00
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val host = new HostIO
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2014-03-30 17:13:05 +02:00
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val mem = new MemIO
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2014-08-25 04:30:53 +02:00
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val tiles = Vec.fill(nTiles){new TileLinkIO}.flip
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val htif = Vec.fill(nTiles){new HTIFIO}.flip
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val incoherent = Vec.fill(nTiles){Bool()}.asInput
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val mem_backup = new MemSerializedIO(htifW)
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2012-10-09 22:05:56 +02:00
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val mem_backup_en = Bool(INPUT)
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}
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2014-08-25 04:30:53 +02:00
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// Used to hash physical addresses to banks
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require(params(BankIdLSB) + log2Up(params(NBanks)) < params(MIFAddrBits))
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def addrToBank(addr: Bits): UInt = {
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if(nBanks > 1) addr( lsb + log2Up(nBanks) - 1, lsb)
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else UInt(0)
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2013-04-23 02:38:13 +02:00
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}
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2014-08-25 04:30:53 +02:00
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val htif = Module(new HTIF(CSRs.reset)) // One HTIF module per chip
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val outmemsys = Module(new OuterMemorySystem) // NoC, LLC and SerDes
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// Wire outer mem system to tiles and htif, adding
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// networking headers and endpoint queues
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(outmemsys.io.tiles :+ outmemsys.io.htif) // Collect outward-facing TileLink ports
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.zip(io.tiles :+ htif.io.mem) // Zip them with matching ports from clients
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.zipWithIndex // Index them
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.map { case ((outer, client), i) => // Then use the index and bank hash to
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// overwrite the networking header
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outer.acquire <> Queue(TileLinkHeaderOverwriter(client.acquire, i, nBanks, addrToBank _))
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outer.release <> Queue(TileLinkHeaderOverwriter(client.release, i, nBanks, addrToBank _))
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2014-04-27 04:16:37 +02:00
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outer.finish <> Queue(TileLinkHeaderOverwriter(client.finish, i, true))
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2013-03-20 22:11:54 +01:00
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client.grant <> Queue(outer.grant, 1, pipe = true)
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client.probe <> Queue(outer.probe)
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2014-08-25 04:30:53 +02:00
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}
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outmemsys.io.incoherent := (io.incoherent :+ Bool(true).asInput)
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2013-09-25 10:21:41 +02:00
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2014-08-25 04:30:53 +02:00
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// Wire the htif to the memory port(s) and host interface
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2013-09-25 10:21:41 +02:00
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io.host.debug_stats_pcr := htif.io.host.debug_stats_pcr
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2014-08-25 04:30:53 +02:00
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htif.io.cpu <> io.htif
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outmemsys.io.mem <> io.mem
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if(params(UseBackupMemoryPort)) {
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outmemsys.io.mem_backup_en := io.mem_backup_en
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VLSIUtils.padOutHTIFWithDividedClock(htif.io, outmemsys.io.mem_backup,
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io.mem_backup, io.host, io.mem_backup_en, htifW)
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} else {
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htif.io.host.out <> io.host.out
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htif.io.host.in <> io.host.in
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}
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2012-10-09 22:05:56 +02:00
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}
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2014-08-25 04:30:53 +02:00
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class TopIO extends Bundle {
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val host = new HostIO
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2014-03-30 17:13:05 +02:00
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val mem = new MemIO
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2012-10-09 22:05:56 +02:00
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val mem_backup_en = Bool(INPUT)
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2012-10-23 12:31:34 +02:00
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val in_mem_ready = Bool(OUTPUT)
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val in_mem_valid = Bool(INPUT)
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val out_mem_ready = Bool(INPUT)
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val out_mem_valid = Bool(OUTPUT)
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2012-10-09 22:05:56 +02:00
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}
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2014-08-25 04:30:53 +02:00
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class Top extends Module with TopLevelParameters {
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val io = new TopIO
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2014-08-08 21:27:47 +02:00
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val resetSigs = Vec.fill(nTiles){Bool()}
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2014-08-23 10:26:03 +02:00
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val tileList = (0 until nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))))
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val uncore = Module(new Uncore)
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2014-08-08 21:27:47 +02:00
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for (i <- 0 until nTiles) {
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2012-10-09 22:05:56 +02:00
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val hl = uncore.io.htif(i)
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val tl = uncore.io.tiles(i)
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2013-01-07 23:19:55 +01:00
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val il = uncore.io.incoherent(i)
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2012-10-19 02:51:41 +02:00
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2012-12-13 01:41:21 +01:00
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resetSigs(i) := hl.reset
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val tile = tileList(i)
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2014-04-27 04:16:37 +02:00
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2013-03-20 22:11:54 +01:00
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tile.io.tilelink <> tl
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il := hl.reset
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2014-04-27 04:16:37 +02:00
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tile.io.host.id := UInt(i)
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2013-08-16 01:37:58 +02:00
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tile.io.host.reset := Reg(next=Reg(next=hl.reset))
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2014-08-25 04:30:53 +02:00
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tile.io.host.pcr_req <> Queue(hl.pcr_req)
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hl.pcr_rep <> Queue(tile.io.host.pcr_rep)
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hl.ipi_req <> Queue(tile.io.host.ipi_req)
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tile.io.host.ipi_rep <> Queue(hl.ipi_rep)
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2013-09-25 10:21:41 +02:00
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hl.debug_stats_pcr := tile.io.host.debug_stats_pcr
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2012-10-09 22:05:56 +02:00
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}
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io.host <> uncore.io.host
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io.mem <> uncore.io.mem
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2014-08-25 04:30:53 +02:00
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if(params(UseBackupMemoryPort)) {
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uncore.io.mem_backup.resp.valid := io.in_mem_valid
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io.out_mem_valid := uncore.io.mem_backup.req.valid
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uncore.io.mem_backup.req.ready := io.out_mem_ready
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io.mem_backup_en <> uncore.io.mem_backup_en
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}
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2012-10-09 22:05:56 +02:00
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}
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