1
0
rocket-chip/groundtest/src/main/scala/Tile.scala

139 lines
4.2 KiB
Scala
Raw Normal View History

package groundtest
2015-10-27 05:37:35 +01:00
import Chisel._
import rocket._
import uncore.tilelink._
2016-05-03 03:25:02 +02:00
import junctions._
2015-10-27 05:37:35 +01:00
import scala.util.Random
import scala.collection.mutable.ListBuffer
2015-11-19 07:54:05 +01:00
import cde.{Parameters, Field}
case object BuildGroundTest extends Field[Parameters => GroundTest]
2015-10-27 05:37:35 +01:00
case class GroundTestTileSettings(
uncached: Int = 0, cached: Int = 0, ptw: Int = 0,
maxXacts: Int = 1, csrs: Int = 0)
case object GroundTestKey extends Field[Seq[GroundTestTileSettings]]
case object GroundTestId extends Field[Int]
trait HasGroundTestConstants {
val timeoutCodeBits = 4
val errorCodeBits = 4
}
trait HasGroundTestParameters extends HasAddrMapParameters {
implicit val p: Parameters
val tileId = p(GroundTestId)
val tileSettings = p(GroundTestKey)(tileId)
val nUncached = tileSettings.uncached
val nCached = tileSettings.cached
val nPTW = tileSettings.ptw
val memStart = addrMap("mem").start
val memStartBlock = memStart >> p(CacheBlockOffsetBits)
}
2015-11-19 05:53:36 +01:00
class DummyPTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
val io = new Bundle {
val requestors = Vec(n, new TLBPTWIO).flip
}
val req_arb = Module(new RRArbiter(new PTWReq, n))
req_arb.io.in <> io.requestors.map(_.req)
req_arb.io.out.ready := Bool(true)
def vpn_to_ppn(vpn: UInt): UInt = vpn(ppnBits - 1, 0)
class QueueChannel extends ParameterizedBundle()(p) {
val ppn = UInt(width = ppnBits)
val chosen = UInt(width = log2Up(n))
}
val s1_ppn = vpn_to_ppn(req_arb.io.out.bits.addr)
val s2_ppn = RegEnable(s1_ppn, req_arb.io.out.valid)
val s2_chosen = RegEnable(req_arb.io.chosen, req_arb.io.out.valid)
val s2_valid = Reg(next = req_arb.io.out.valid)
val s2_resp = Wire(new PTWResp)
s2_resp.pte.ppn := s2_ppn
s2_resp.pte.reserved_for_software := UInt(0)
2016-01-20 20:39:40 +01:00
s2_resp.pte.d := Bool(true)
2016-07-06 12:20:41 +02:00
s2_resp.pte.a := Bool(false)
s2_resp.pte.g := Bool(false)
s2_resp.pte.u := Bool(true)
s2_resp.pte.r := Bool(true)
s2_resp.pte.w := Bool(true)
s2_resp.pte.x := Bool(false)
2015-11-19 05:53:36 +01:00
s2_resp.pte.v := Bool(true)
io.requestors.zipWithIndex.foreach { case (requestor, i) =>
requestor.resp.valid := s2_valid && s2_chosen === UInt(i)
requestor.resp.bits := s2_resp
requestor.status.vm := UInt("b01000")
requestor.status.prv := UInt(PRV.S)
requestor.invalidate := Bool(false)
2015-11-19 05:53:36 +01:00
}
}
class GroundTestStatus extends Bundle with HasGroundTestConstants {
val finished = Bool(OUTPUT)
val timeout = Valid(UInt(width = timeoutCodeBits))
val error = Valid(UInt(width = errorCodeBits))
}
class GroundTestIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
with HasGroundTestParameters {
val cache = Vec(nCached, new HellaCacheIO)
val mem = Vec(nUncached, new ClientUncachedTileLinkIO)
val ptw = Vec(nPTW, new TLBPTWIO)
val status = new GroundTestStatus
2015-11-19 07:54:05 +01:00
}
2016-05-03 03:25:02 +02:00
abstract class GroundTest(implicit val p: Parameters) extends Module
with HasGroundTestParameters {
2015-11-19 07:54:05 +01:00
val io = new GroundTestIO
}
class GroundTestTile(resetSignal: Bool)
(implicit val p: Parameters)
extends Tile(resetSignal = resetSignal)(p)
with HasGroundTestParameters {
2015-10-27 05:37:35 +01:00
val test = p(BuildGroundTest)(dcacheParams)
2015-11-19 05:53:36 +01:00
val ptwPorts = ListBuffer.empty ++= test.io.ptw
val memPorts = ListBuffer.empty ++= test.io.mem
if (nCached > 0) {
val dcache_io =
if (p(NMSHRs) == 0) Module(new DCache()(dcacheParams)).io
else Module(new HellaCache()(dcacheParams)).io
val dcacheArb = Module(new HellaCacheArbiter(nCached)(dcacheParams))
dcacheArb.io.requestor.zip(test.io.cache).foreach {
case (requestor, cache) =>
val dcacheIF = Module(new SimpleHellaCacheIF()(dcacheParams))
dcacheIF.io.requestor <> cache
requestor <> dcacheIF.io.cache
}
dcache_io.cpu <> dcacheArb.io.mem
io.cached.head <> dcache_io.mem
2015-10-27 05:37:35 +01:00
// SimpleHellaCacheIF leaves invalidate_lr dangling, so we wire it to false
dcache_io.cpu.invalidate_lr := Bool(false)
ptwPorts += dcache_io.ptw
}
2016-05-03 03:25:02 +02:00
when (test.io.status.finished) { stop() }
2016-05-03 03:25:02 +02:00
if (ptwPorts.size > 0) {
val ptw = Module(new DummyPTW(ptwPorts.size))
ptw.io.requestors <> ptwPorts
}
require(memPorts.size == io.uncached.size)
if (memPorts.size > 0) {
io.uncached <> memPorts
}
2015-10-27 05:37:35 +01:00
}