2015-10-27 05:37:35 +01:00
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package groundtest
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import Chisel._
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import rocket._
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import uncore._
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2016-05-03 03:25:02 +02:00
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import junctions._
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2015-10-27 05:37:35 +01:00
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import scala.util.Random
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2016-06-14 01:17:11 +02:00
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import scala.collection.mutable.ListBuffer
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2015-11-19 07:54:05 +01:00
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import cde.{Parameters, Field}
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case object BuildGroundTest extends Field[(Int, Parameters) => GroundTest]
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case object GroundTestMaxXacts extends Field[Int]
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2016-03-23 04:00:28 +01:00
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case object GroundTestCSRs extends Field[Seq[Int]]
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2016-05-04 05:20:52 +02:00
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case object TohostAddr extends Field[BigInt]
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2015-10-27 05:37:35 +01:00
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2016-06-14 01:17:11 +02:00
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case object GroundTestCachedClients extends Field[Int]
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case object GroundTestUncachedClients extends Field[Int]
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case object GroundTestNPTW extends Field[Int]
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trait HasGroundTestParameters extends HasAddrMapParameters {
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implicit val p: Parameters
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val nUncached = p(GroundTestUncachedClients)
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val nCached = p(GroundTestCachedClients)
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val nPTW = p(GroundTestNPTW)
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val memStart = addrMap("mem").start
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val memStartBlock = memStart >> p(CacheBlockOffsetBits)
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}
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2015-11-19 05:53:36 +01:00
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class DummyPTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
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val io = new Bundle {
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val requestors = Vec(n, new TLBPTWIO).flip
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}
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val req_arb = Module(new RRArbiter(new PTWReq, n))
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req_arb.io.in <> io.requestors.map(_.req)
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req_arb.io.out.ready := Bool(true)
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def vpn_to_ppn(vpn: UInt): UInt = vpn(ppnBits - 1, 0)
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class QueueChannel extends ParameterizedBundle()(p) {
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val ppn = UInt(width = ppnBits)
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val chosen = UInt(width = log2Up(n))
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}
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val s1_ppn = vpn_to_ppn(req_arb.io.out.bits.addr)
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val s2_ppn = RegEnable(s1_ppn, req_arb.io.out.valid)
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val s2_chosen = RegEnable(req_arb.io.chosen, req_arb.io.out.valid)
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val s2_valid = Reg(next = req_arb.io.out.valid)
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val s2_resp = Wire(new PTWResp)
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s2_resp.pte.ppn := s2_ppn
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s2_resp.pte.reserved_for_software := UInt(0)
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2016-01-20 20:39:40 +01:00
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s2_resp.pte.d := Bool(true)
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2015-11-19 05:53:36 +01:00
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s2_resp.pte.r := Bool(false)
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2016-01-20 20:39:40 +01:00
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s2_resp.pte.typ := UInt("b0101")
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2015-11-19 05:53:36 +01:00
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s2_resp.pte.v := Bool(true)
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io.requestors.zipWithIndex.foreach { case (requestor, i) =>
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requestor.resp.valid := s2_valid && s2_chosen === UInt(i)
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requestor.resp.bits := s2_resp
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requestor.status.vm := UInt("b01000")
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2016-03-15 01:55:19 +01:00
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requestor.status.prv := UInt(PRV.S)
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2016-03-23 03:59:58 +01:00
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requestor.invalidate := Bool(false)
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2015-11-19 05:53:36 +01:00
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}
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}
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2016-06-14 01:17:11 +02:00
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class GroundTestIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
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with HasGroundTestParameters {
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val cache = Vec(nCached, new HellaCacheIO)
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val mem = Vec(nUncached, new ClientUncachedTileLinkIO)
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val ptw = Vec(nPTW, new TLBPTWIO)
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2015-11-19 07:54:05 +01:00
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val finished = Bool(OUTPUT)
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}
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2015-11-01 01:43:25 +01:00
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2016-05-03 03:25:02 +02:00
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abstract class GroundTest(implicit val p: Parameters) extends Module
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2016-06-14 01:17:11 +02:00
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with HasGroundTestParameters {
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2015-11-19 07:54:05 +01:00
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val io = new GroundTestIO
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}
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2015-11-01 01:43:25 +01:00
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2015-11-19 07:54:05 +01:00
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class GroundTestTile(id: Int, resetSignal: Bool)
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2016-06-14 01:17:11 +02:00
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(implicit val p: Parameters)
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extends Tile(resetSignal = resetSignal)(p)
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with HasGroundTestParameters {
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2015-10-27 05:37:35 +01:00
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2015-11-19 07:54:05 +01:00
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val test = p(BuildGroundTest)(id, dcacheParams)
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2015-11-19 05:53:36 +01:00
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2016-06-14 01:17:11 +02:00
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val ptwPorts = ListBuffer.empty ++= test.io.ptw
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val memPorts = ListBuffer.empty ++= test.io.mem
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if (nCached > 0) {
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val dcache = Module(new HellaCache()(dcacheParams))
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val dcacheArb = Module(new HellaCacheArbiter(nCached)(dcacheParams))
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dcacheArb.io.requestor.zip(test.io.cache).foreach {
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case (requestor, cache) =>
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val dcacheIF = Module(new SimpleHellaCacheIF()(dcacheParams))
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dcacheIF.io.requestor <> cache
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requestor <> dcacheIF.io.cache
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}
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dcache.io.cpu <> dcacheArb.io.mem
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io.cached.head <> dcache.io.mem
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2015-10-27 05:37:35 +01:00
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2016-06-14 01:17:11 +02:00
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// SimpleHellaCacheIF leaves invalidate_lr dangling, so we wire it to false
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dcache.io.cpu.invalidate_lr := Bool(false)
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2016-05-25 14:27:12 +02:00
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2016-06-14 01:17:11 +02:00
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ptwPorts += dcache.io.ptw
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}
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2016-05-03 03:25:02 +02:00
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2016-05-03 22:09:22 +02:00
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// Only Tile 0 needs to write tohost
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if (id == 0) {
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2016-06-23 21:16:37 +02:00
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when (test.io.finished) {
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stop()
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}
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2016-06-14 01:17:11 +02:00
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}
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2016-05-03 03:25:02 +02:00
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2016-06-14 01:17:11 +02:00
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if (ptwPorts.size > 0) {
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val ptw = Module(new DummyPTW(ptwPorts.size))
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ptw.io.requestors <> ptwPorts
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}
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require(memPorts.size == io.uncached.size)
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if (memPorts.size > 0) {
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io.uncached <> memPorts
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}
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2015-10-27 05:37:35 +01:00
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}
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