2012-02-26 02:09:26 +01:00
|
|
|
package rocket
|
2011-10-26 08:02:47 +02:00
|
|
|
|
|
|
|
import Chisel._
|
|
|
|
import Node._;
|
|
|
|
import Constants._;
|
|
|
|
|
2012-02-20 08:15:45 +01:00
|
|
|
class ioTop(htif_width: Int) extends Bundle {
|
2011-10-26 08:02:47 +02:00
|
|
|
val debug = new ioDebug();
|
2012-02-20 08:15:45 +01:00
|
|
|
val host = new ioHost(htif_width);
|
2012-02-29 12:08:04 +01:00
|
|
|
val mem = new ioMem
|
2011-10-26 08:02:47 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
class Top() extends Component {
|
2012-02-20 08:15:45 +01:00
|
|
|
|
|
|
|
val htif_width = 16
|
|
|
|
val io = new ioTop(htif_width);
|
|
|
|
val htif = new rocketHTIF(htif_width, 1)
|
2011-10-26 08:02:47 +02:00
|
|
|
|
2012-02-23 04:30:03 +01:00
|
|
|
val cpu = new rocketProc(resetSignal = htif.io.cpu(0).reset);
|
2012-01-25 01:51:30 +01:00
|
|
|
val icache = new rocketICache(128, 2); // 128 sets x 2 ways
|
2011-10-26 08:02:47 +02:00
|
|
|
val icache_pf = new rocketIPrefetcher();
|
2012-02-16 21:34:51 +01:00
|
|
|
val dcache = new HellaCacheUniproc();
|
2011-10-26 08:02:47 +02:00
|
|
|
|
2012-02-29 12:08:04 +01:00
|
|
|
val arbiter = new rocketMemArbiter(3 + (if (HAVE_VEC) 1 else 0));
|
2012-02-20 09:51:48 +01:00
|
|
|
arbiter.io.requestor(0) <> dcache.io.mem
|
|
|
|
arbiter.io.requestor(1) <> icache_pf.io.mem
|
2012-02-29 12:08:04 +01:00
|
|
|
arbiter.io.requestor(2) <> htif.io.mem
|
|
|
|
|
|
|
|
val hub = new CoherenceHubNull
|
|
|
|
// connect tile to hub (figure out how to do this more compactly)
|
|
|
|
val xact_init_q = (new queue(2)) { new TransactionInit }
|
|
|
|
xact_init_q.io.enq <> arbiter.io.mem.xact_init
|
|
|
|
xact_init_q.io.deq <> hub.io.tile.xact_init
|
|
|
|
val xact_init_data_q = (new queue(2)) { new TransactionInitData }
|
|
|
|
xact_init_data_q.io.enq <> arbiter.io.mem.xact_init_data
|
|
|
|
xact_init_data_q.io.deq <> hub.io.tile.xact_init_data
|
|
|
|
val xact_rep_q = (new queue(1, pipe = true)) { new TransactionReply }
|
|
|
|
xact_rep_q.io.enq <> hub.io.tile.xact_rep
|
|
|
|
xact_rep_q.io.deq <> arbiter.io.mem.xact_rep
|
|
|
|
// connect hub to memory
|
|
|
|
val mem_req_q = (new queue(2)) { new MemReqCmd }
|
|
|
|
mem_req_q.io.enq <> hub.io.mem.req_cmd
|
|
|
|
mem_req_q.io.deq <> io.mem.req_cmd
|
|
|
|
val mem_req_data_q = (new queue(2)) { new MemData }
|
|
|
|
mem_req_data_q.io.enq <> hub.io.mem.req_data
|
|
|
|
mem_req_data_q.io.deq <> io.mem.req_data
|
|
|
|
hub.io.mem.resp.valid := Reg(io.mem.resp.valid, resetVal = Bool(false))
|
|
|
|
hub.io.mem.resp.bits := Reg(io.mem.resp.bits)
|
|
|
|
|
2011-10-26 08:02:47 +02:00
|
|
|
|
2012-02-22 00:53:19 +01:00
|
|
|
if (HAVE_VEC)
|
|
|
|
{
|
|
|
|
val vicache = new rocketICache(128, 2); // 128 sets x 2 ways
|
2012-02-29 12:08:04 +01:00
|
|
|
arbiter.io.requestor(3) <> vicache.io.mem
|
2012-02-22 00:53:19 +01:00
|
|
|
cpu.io.vimem <> vicache.io.cpu;
|
|
|
|
}
|
|
|
|
|
2012-02-20 08:15:45 +01:00
|
|
|
htif.io.host <> io.host
|
|
|
|
cpu.io.host <> htif.io.cpu(0);
|
2012-01-23 18:51:35 +01:00
|
|
|
cpu.io.debug <> io.debug;
|
2011-10-26 08:02:47 +02:00
|
|
|
|
2012-02-18 02:56:01 +01:00
|
|
|
icache_pf.io.invalidate := cpu.io.imem.invalidate
|
2011-10-26 08:02:47 +02:00
|
|
|
icache.io.mem <> icache_pf.io.icache;
|
|
|
|
cpu.io.imem <> icache.io.cpu;
|
|
|
|
cpu.io.dmem <> dcache.io.cpu;
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
object top_main {
|
|
|
|
def main(args: Array[String]) = {
|
2012-02-14 11:53:43 +01:00
|
|
|
chiselMain(args, () => new Top());
|
2011-10-26 08:02:47 +02:00
|
|
|
}
|
|
|
|
}
|