Load 32 MiB bootimage from a 2048 sector offset (first partiton)

More than one core does not fit on the ml507 and is more than enough for
booting linux and executing basic utilities.

.gitmodules

@@ -1,9 +1,9 @@
 [submodule "rocket-chip"]
 	path = rocket-chip
-	url = https://github.com/ucb-bar/rocket-chip.git
+	url = https://git.tiband.de/riscv/rocket-chip.git
 [submodule "sifive-blocks"]
 	path = sifive-blocks
-	url = https://github.com/sifive/sifive-blocks.git
+	url = https://git.tiband.de/riscv/sifive-blocks.git
 [submodule "fpga-shells"]
 	path = fpga-shells
-	url = https://github.com/sifive/fpga-shells
+	url = https://git.tiband.de/riscv/fpga-shells.git

Makefile.u500ml507devkit

@@ -0,0 +1,24 @@
+# See LICENSE for license details.
+base_dir := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
+BUILD_DIR := $(base_dir)/builds/u500ml507devkit
+FPGA_DIR := $(base_dir)/fpga-shells/xilinx
+MODEL := U500ML507DevKitFPGAChip
+PROJECT := sifive.freedom.unleashed.u500ml507devkit
+export CONFIG_PROJECT := sifive.freedom.unleashed.u500ml507devkit
+export CONFIG := U500ML507DevKitConfig
+export BOARD := ml507
+export BOOTROM_DIR := $(base_dir)/bootrom/sdboot
+
+rocketchip_dir := $(base_dir)/rocket-chip
+sifiveblocks_dir := $(base_dir)/sifive-blocks
+VSRCS := \
+	$(rocketchip_dir)/vsrc/AsyncResetReg.v \
+	$(rocketchip_dir)/vsrc/plusarg_reader.v \
+	$(sifiveblocks_dir)/vsrc/SRLatch.v \
+	$(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
+	$(FPGA_DIR)/$(BOARD)/vsrc/sdio.v \
+	$(FPGA_DIR)/$(BOARD)/vsrc/ml507reset.v \
+	$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v \
+	$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v
+
+include common.mk

bootrom/sdboot/kprintf.h

@@ -33,6 +33,9 @@ static inline void kputc(char c)
 	while ((int32_t)(*tx) < 0);
 	*tx = c;
 #endif
+	volatile uint32_t *term = (void *) 0x64003000; // Terminal (32 bit)
+	while ((int32_t)(*term) < 0);
+	*term = c;
 }
 
 extern void kputs(const char *);

bootrom/sdboot/sd.c

@@ -10,9 +10,13 @@
 
 #define MAX_CORES 8
 
-#define PAYLOAD_SIZE	(16 << 11)
+//#define PAYLOAD_START 0
+//#define PAYLOAD_CRC7 0xE1
+#define PAYLOAD_START 2048
+#define PAYLOAD_CRC7 0x51
+#define PAYLOAD_SIZE	(16 << 12)
 
-#define F_CLK 50000000UL
+#define F_CLK 60000000UL
 
 static volatile uint32_t * const spi = (void *)(SPI_CTRL_ADDR);
 
@@ -163,7 +167,7 @@ static int copy(void)
 	kprintf("LOADING  ");
 
 	REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 20000000UL);
-	if (sd_cmd(0x52, 0, 0xE1) != 0x00) {
+	if (sd_cmd(0x52, PAYLOAD_START, PAYLOAD_CRC7) != 0x00) {
 		sd_cmd_end();
 		return 1;
 	}

common.mk

@@ -63,7 +63,7 @@ endif
 verilog: $(verilog)
 
 romgen := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v
-$(romgen): $(verilog)
+$(romgen): $(verilog) $(BOOTROM_DIR)
 ifneq ($(BOOTROM_DIR),"")
 	$(MAKE) -C $(BOOTROM_DIR) romgen
 	mv $(BUILD_DIR)/rom.v $@

src/main/scala/unleashed/u500ml507devkit/Config.scala

@@ -0,0 +1,58 @@
+// See LICENSE for license details.
+package sifive.freedom.unleashed.u500ml507devkit
+
+import freechips.rocketchip.config._
+import freechips.rocketchip.subsystem._
+import freechips.rocketchip.devices.debug._
+import freechips.rocketchip.devices.tilelink._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.system._
+import freechips.rocketchip.tile._
+
+import sifive.blocks.devices.gpio._
+import sifive.blocks.devices.spi._
+import sifive.blocks.devices.uart._
+import sifive.blocks.devices.terminal._
+
+import sifive.fpgashells.devices.xilinx.xilinxml507mig._
+
+// Default FreedomUML507Config
+class FreedomUML507Config extends Config(
+  new WithoutTLMonitors      ++
+  new WithJtagDTM            ++
+  new WithClockFrequency(60000000) ++ // 60 MHz
+  new WithNMemoryChannels(1) ++
+  new WithNSmallLinuxCores(1)       ++
+  new BaseConfig
+)
+
+// Freedom U500 ML507 Dev Kit Peripherals
+class U500ML507DevKitPeripherals extends Config((site, here, up) => {
+  case PeripheryUARTKey => List(
+    UARTParams(address = BigInt(0x64000000L)))
+  case PeripherySPIKey => List(
+    SPIParams(rAddress = BigInt(0x64001000L)))
+  case PeripheryGPIOKey => List(
+    GPIOParams(address = BigInt(0x64002000L), width = 8))
+  case PeripheryTerminalKey =>
+    TerminalParams(address = BigInt(0x64003000L))
+  case PeripheryMaskROMKey => List(
+    MaskROMParams(address = 0x10000, name = "BootROM"))
+})
+
+// Freedom U500 ML507 Dev Kit
+class U500ML507DevKitConfig extends Config(
+  new WithNExtTopInterrupts(0)   ++
+  new U500ML507DevKitPeripherals ++
+  new FreedomUML507Config().alter((site,here,up) => {
+    case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff)), maxAtomic=site(XLen)/8, maxTransfer=128)
+    case MemoryML507Key => XilinxML507MIGParams(address = Seq(AddressSet(0x80000000L,0x10000000L-1))) // 256 MiB
+    case DTSTimebase => BigInt(1000000)
+    case ExtMem => up(ExtMem).copy(size = 0x10000000L)
+    case JtagDTMKey => new JtagDTMConfig (
+      idcodeVersion = 2,      // 1 was legacy (FE310-G000, Acai).
+      idcodePartNum = 0x000,  // Decided to simplify.
+      idcodeManufId = 0x489,  // As Assigned by JEDEC to SiFive. Only used in wrappers / test harnesses.
+      debugIdleCycles = 5)    // Reasonable guess for synchronization
+  })
+)

src/main/scala/unleashed/u500ml507devkit/FPGAChip.scala

@@ -0,0 +1,66 @@
+// See LICENSE for license details.
+package sifive.freedom.unleashed.u500ml507devkit
+
+import Chisel._
+import chisel3.experimental.{withClockAndReset}
+
+import freechips.rocketchip.config._
+import freechips.rocketchip.diplomacy._
+
+import sifive.blocks.devices.gpio._
+import sifive.blocks.devices.pinctrl.{BasePin}
+
+import sifive.fpgashells.shell.xilinx.ml507shell._
+
+//-------------------------------------------------------------------------
+// PinGen
+//-------------------------------------------------------------------------
+
+object PinGen {
+  def apply(): BasePin = {
+    new BasePin()
+  }
+}
+
+//-------------------------------------------------------------------------
+// U500ML507DevKitFPGAChip
+//-------------------------------------------------------------------------
+
+class U500ML507DevKitFPGAChip(implicit override val p: Parameters)
+    extends ML507Shell
+    with HasDebugJTAG {
+
+  //-----------------------------------------------------------------------
+  // DUT
+  //-----------------------------------------------------------------------
+
+  withClockAndReset(dut_clock, dut_reset) {
+    val dut = Module(LazyModule(new U500ML507DevKitSystem).module)
+
+    //---------------------------------------------------------------------
+    // Connect peripherals
+    //---------------------------------------------------------------------
+
+    connectTerminal (dut)
+    connectDDRMemory(dut)
+    connectDebugJTAG(dut)
+    connectSPI      (dut)
+    connectUART     (dut)
+
+    //---------------------------------------------------------------------
+    // GPIO
+    //---------------------------------------------------------------------
+
+    val gpioParams = p(PeripheryGPIOKey)
+    val gpio_pins = Wire(new GPIOPins(() => PinGen(), gpioParams(0)))
+
+    GPIOPinsFromPort(gpio_pins, dut.gpio(0))
+
+    gpio_pins.pins.zipWithIndex.foreach {
+      case(pin, idx) =>
+        pin.i.ival := dip(idx)
+        led(idx) := pin.o.oval
+    }
+  }
+
+}

src/main/scala/unleashed/u500ml507devkit/System.scala

@@ -0,0 +1,48 @@
+// See LICENSE for license details.
+package sifive.freedom.unleashed.u500ml507devkit
+
+import Chisel._
+
+import freechips.rocketchip.config._
+import freechips.rocketchip.subsystem._
+import freechips.rocketchip.devices.debug._
+import freechips.rocketchip.devices.tilelink._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.system._
+
+import sifive.blocks.devices.gpio._
+import sifive.blocks.devices.spi._
+import sifive.blocks.devices.uart._
+import sifive.blocks.devices.terminal._
+
+import sifive.fpgashells.devices.xilinx.xilinxml507mig._
+
+//-------------------------------------------------------------------------
+// U500ML507DevKitSystem
+//-------------------------------------------------------------------------
+
+class U500ML507DevKitSystem(implicit p: Parameters) extends RocketSubsystem
+    with HasPeripheryMaskROMSlave
+    with HasPeripheryDebug
+    with HasSystemErrorSlave
+    with HasPeripheryUART
+    with HasPeripheryTerminal
+    with HasPeripherySPI
+    with HasPeripheryGPIO
+    with HasMemoryML507 {
+  override lazy val module = new U500ML507DevKitSystemModule(this)
+}
+
+class U500ML507DevKitSystemModule[+L <: U500ML507DevKitSystem](_outer: L)
+  extends RocketSubsystemModuleImp(_outer)
+    with HasRTCModuleImp
+    with HasPeripheryDebugModuleImp
+    with HasPeripheryUARTModuleImp
+    with HasPeripheryTerminalModuleImp
+    with HasPeripherySPIModuleImp
+    with HasPeripheryGPIOModuleImp
+    with HasMemoryML507ModuleImp {
+  // Reset vector is set to the location of the mask rom
+  val maskROMParams = p(PeripheryMaskROMKey)
+  global_reset_vector := maskROMParams(0).address.U
+}