TEST: Read 50 byte from sd card and write to terminal

More than one core does not fit on the ml507 and is more than enough for
booting linux and executing basic utilities.

.gitmodules

@@ -1,9 +1,9 @@
 [submodule "rocket-chip"]
 	path = rocket-chip
-	url = https://github.com/ucb-bar/rocket-chip.git
+	url = https://git.tiband.de/riscv/rocket-chip.git
 [submodule "sifive-blocks"]
 	path = sifive-blocks
-	url = https://github.com/sifive/sifive-blocks.git
+	url = https://git.tiband.de/riscv/sifive-blocks.git
 [submodule "fpga-shells"]
 	path = fpga-shells
-	url = https://github.com/sifive/fpga-shells
+	url = https://git.tiband.de/riscv/fpga-shells.git

Makefile.u500ml507devkit

@@ -0,0 +1,24 @@
+# See LICENSE for license details.
+base_dir := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
+BUILD_DIR := $(base_dir)/builds/u500ml507devkit
+FPGA_DIR := $(base_dir)/fpga-shells/xilinx
+MODEL := U500ML507DevKitFPGAChip
+PROJECT := sifive.freedom.unleashed.u500ml507devkit
+export CONFIG_PROJECT := sifive.freedom.unleashed.u500ml507devkit
+export CONFIG := U500ML507DevKitConfig
+export BOARD := ml507
+export BOOTROM_DIR := $(base_dir)/bootrom/sdboot
+
+rocketchip_dir := $(base_dir)/rocket-chip
+sifiveblocks_dir := $(base_dir)/sifive-blocks
+VSRCS := \
+	$(rocketchip_dir)/vsrc/AsyncResetReg.v \
+	$(rocketchip_dir)/vsrc/plusarg_reader.v \
+	$(sifiveblocks_dir)/vsrc/SRLatch.v \
+	$(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
+	$(FPGA_DIR)/$(BOARD)/vsrc/sdio.v \
+	$(FPGA_DIR)/$(BOARD)/vsrc/ml507reset.v \
+	$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v \
+	$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v
+
+include common.mk

bootrom/sdboot/head.S

@@ -8,7 +8,7 @@
   .globl _prog_start
 _prog_start:
   smp_pause(s1, s2)
-  li sp, (PAYLOAD_DEST + 0x7fff000)
+  li sp, (PAYLOAD_DEST + 0xffff000)
   call main
   smp_resume(s1, s2)
   csrr a0, mhartid

bootrom/sdboot/kprintf.h

@@ -20,7 +20,8 @@ static volatile uint32_t * const uart = (void *)(UART_CTRL_ADDR);
 
 static inline void kputc(char c)
 {
-	volatile uint32_t *tx = &REG32(uart, UART_REG_TXFIFO);
+	//volatile uint32_t *tx = &REG32(uart, UART_REG_TXFIFO);
+	volatile uint32_t *tx = (void *) 0x64003000; // Terminal (32 bit)
 #ifdef __riscv_atomic
 	int32_t r;
 	do {

bootrom/sdboot/sd.c

@@ -12,7 +12,7 @@
 
 #define PAYLOAD_SIZE	(16 << 11)
 
-#define F_CLK 50000000UL
+#define F_CLK 60000000UL
 
 static volatile uint32_t * const spi = (void *)(SPI_CTRL_ADDR);
 
@@ -160,7 +160,8 @@ static int copy(void)
 	int rc = 0;
 
 	dputs("CMD18");
-	kprintf("LOADING  ");
+	//~ kprintf("LOADING  ");
+	kprintf("READ: ");
 
 	REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 20000000UL);
 	if (sd_cmd(0x52, 0, 0xE1) != 0x00) {
@@ -172,14 +173,18 @@ static int copy(void)
 		long n;
 
 		crc = 0;
-		n = 512;
+		//~ n = 512;
+		n = 50;
 		while (sd_dummy() != 0xFE);
 		do {
 			uint8_t x = sd_dummy();
-			*p++ = x;
-			crc = crc16_round(crc, x);
+			kputc(x);
+			//~ *p++ = x;
+			//~ crc = crc16_round(crc, x);
 		} while (--n > 0);
 
+		return 0;
+
 		crc_exp = ((uint16_t)sd_dummy() << 8);
 		crc_exp |= sd_dummy();
 
@@ -202,10 +207,60 @@ static int copy(void)
 	return rc;
 }
 
+// leave room for 2 MiB stack (SP = 8FFFF000)
+#define RAMTEST_START (uint32_t*)(0x80000000)
+#define RAMTEST_END   (uint32_t*)(0x8FDFF000)
+
 int main(void)
 {
-	REG32(uart, UART_REG_TXCTRL) = UART_TXEN;
+	//REG32(uart, UART_REG_TXCTRL) = UART_TXEN;
 
+	//GPIO_REG(GPIO_INPUT_EN) = 0xFF;
+	GPIO_REG(GPIO_OUTPUT_EN) = 0xFF;
+	GPIO_REG(GPIO_OUTPUT_VAL) = 0xFF;
+
+	kprintf("\nFilling RAM from %lx to %lx...\n", RAMTEST_START, RAMTEST_END);
+
+	uint32_t counter = 0;
+	for(uint32_t* ram = RAMTEST_START; ram < RAMTEST_END; ++ram) {
+		*ram = counter++;
+	}
+
+	kprintf("\rChecking RAM...\n");
+
+	counter = 0;
+	uint32_t correct = 0;
+	uint32_t wrong = 0;
+	for(uint32_t* ram = RAMTEST_START; ram < RAMTEST_END; ++ram) {
+		if(*ram != counter) {
+			kprintf("\rMismatch at %lx: read %x, expected %x\n", ram, *ram, counter);
+			++wrong;
+		} else {
+			++correct;
+		}
+		++counter;
+	}
+	kprintf("\rSummary: %x matches, %x mismatches.\n", correct, wrong);
+
+	kprintf("\nTrying to read from SD card...\n");
+
+	kputs("POWERON");
+	sd_poweron();
+	kprintf("sd_cmd0: %hx\n", sd_cmd0());
+	kprintf("sd_cmd8: %hx\n", sd_cmd8());
+	kprintf("sd_acmd41: %hx\n", sd_acmd41());
+	kprintf("sd_cmd58: %hx\n", sd_cmd58());
+	kprintf("sd_cmd16: %hx\n", sd_cmd16());
+	kprintf("\ncopy: %hx\n", copy());
+
+	while(1) {
+		//uint8_t dip_value = GPIO_REG(GPIO_INPUT_VAL) & 0b01111111;
+		//kprintf("dip value: %hx, ram value: %c\n", dip_value, ram[dip_value]);
+
+		GPIO_REG(GPIO_OUTPUT_VAL) ^= 0xFF;
+	}
+	return 0;
+/*
 	kputs("INIT");
 	sd_poweron();
 	if (sd_cmd0() ||
@@ -221,5 +276,5 @@ int main(void)
 	kputs("BOOT");
 
 	__asm__ __volatile__ ("fence.i" : : : "memory");
-	return 0;
+	return 0;*/
 }

src/main/scala/unleashed/u500ml507devkit/Config.scala

@@ -0,0 +1,58 @@
+// See LICENSE for license details.
+package sifive.freedom.unleashed.u500ml507devkit
+
+import freechips.rocketchip.config._
+import freechips.rocketchip.subsystem._
+import freechips.rocketchip.devices.debug._
+import freechips.rocketchip.devices.tilelink._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.system._
+import freechips.rocketchip.tile._
+
+import sifive.blocks.devices.gpio._
+import sifive.blocks.devices.spi._
+import sifive.blocks.devices.uart._
+import sifive.blocks.devices.terminal._
+
+import sifive.fpgashells.devices.xilinx.xilinxml507mig._
+
+// Default FreedomUML507Config
+class FreedomUML507Config extends Config(
+  new WithoutTLMonitors      ++
+  new WithJtagDTM            ++
+  new WithNMemoryChannels(1) ++
+  new WithNBigCores(1)       ++
+  new BaseConfig
+)
+
+// Freedom U500 ML507 Dev Kit Peripherals
+class U500ML507DevKitPeripherals extends Config((site, here, up) => {
+  case PeripheryUARTKey => List(
+    UARTParams(address = BigInt(0x64000000L)))
+  case PeripherySPIKey => List(
+    SPIParams(rAddress = BigInt(0x64001000L)))
+  case PeripheryGPIOKey => List(
+    GPIOParams(address = BigInt(0x64002000L), width = 8))
+  case PeripheryTerminalKey =>
+    TerminalParams(address = BigInt(0x64003000L))
+  case PeripheryMaskROMKey => List(
+    MaskROMParams(address = 0x10000, name = "BootROM"))
+})
+
+// Freedom U500 ML507 Dev Kit
+class U500ML507DevKitConfig extends Config(
+  new WithNExtTopInterrupts(0)   ++
+  new U500ML507DevKitPeripherals ++
+  new FreedomUML507Config().alter((site,here,up) => {
+    case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff)), maxAtomic=site(XLen)/8, maxTransfer=128)
+    case PeripheryBusKey => up(PeripheryBusKey, site).copy(frequency = 60000000) // 60 MHz clock
+    case MemoryML507Key => XilinxML507MIGParams(address = Seq(AddressSet(0x80000000L,0x10000000L-1))) // 256 MiB
+    case DTSTimebase => BigInt(1000000)
+    case ExtMem => up(ExtMem).copy(size = 0x10000000L)
+    case JtagDTMKey => new JtagDTMConfig (
+      idcodeVersion = 2,      // 1 was legacy (FE310-G000, Acai).
+      idcodePartNum = 0x000,  // Decided to simplify.
+      idcodeManufId = 0x489,  // As Assigned by JEDEC to SiFive. Only used in wrappers / test harnesses.
+      debugIdleCycles = 5)    // Reasonable guess for synchronization
+  })
+)

src/main/scala/unleashed/u500ml507devkit/FPGAChip.scala

@@ -0,0 +1,66 @@
+// See LICENSE for license details.
+package sifive.freedom.unleashed.u500ml507devkit
+
+import Chisel._
+import chisel3.experimental.{withClockAndReset}
+
+import freechips.rocketchip.config._
+import freechips.rocketchip.diplomacy._
+
+import sifive.blocks.devices.gpio._
+import sifive.blocks.devices.pinctrl.{BasePin}
+
+import sifive.fpgashells.shell.xilinx.ml507shell._
+
+//-------------------------------------------------------------------------
+// PinGen
+//-------------------------------------------------------------------------
+
+object PinGen {
+  def apply(): BasePin = {
+    new BasePin()
+  }
+}
+
+//-------------------------------------------------------------------------
+// U500ML507DevKitFPGAChip
+//-------------------------------------------------------------------------
+
+class U500ML507DevKitFPGAChip(implicit override val p: Parameters)
+    extends ML507Shell
+    with HasDebugJTAG {
+
+  //-----------------------------------------------------------------------
+  // DUT
+  //-----------------------------------------------------------------------
+
+  withClockAndReset(dut_clock, dut_reset) {
+    val dut = Module(LazyModule(new U500ML507DevKitSystem).module)
+
+    //---------------------------------------------------------------------
+    // Connect peripherals
+    //---------------------------------------------------------------------
+
+    connectTerminal (dut)
+    connectDDRMemory(dut)
+    connectDebugJTAG(dut)
+    connectSPI      (dut)
+    connectUART     (dut)
+
+    //---------------------------------------------------------------------
+    // GPIO
+    //---------------------------------------------------------------------
+
+    val gpioParams = p(PeripheryGPIOKey)
+    val gpio_pins = Wire(new GPIOPins(() => PinGen(), gpioParams(0)))
+
+    GPIOPinsFromPort(gpio_pins, dut.gpio(0))
+
+    gpio_pins.pins.zipWithIndex.foreach {
+      case(pin, idx) =>
+        pin.i.ival := dip(idx)
+        led(idx) := pin.o.oval
+    }
+  }
+
+}

src/main/scala/unleashed/u500ml507devkit/System.scala

@@ -0,0 +1,48 @@
+// See LICENSE for license details.
+package sifive.freedom.unleashed.u500ml507devkit
+
+import Chisel._
+
+import freechips.rocketchip.config._
+import freechips.rocketchip.subsystem._
+import freechips.rocketchip.devices.debug._
+import freechips.rocketchip.devices.tilelink._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.system._
+
+import sifive.blocks.devices.gpio._
+import sifive.blocks.devices.spi._
+import sifive.blocks.devices.uart._
+import sifive.blocks.devices.terminal._
+
+import sifive.fpgashells.devices.xilinx.xilinxml507mig._
+
+//-------------------------------------------------------------------------
+// U500ML507DevKitSystem
+//-------------------------------------------------------------------------
+
+class U500ML507DevKitSystem(implicit p: Parameters) extends RocketSubsystem
+    with HasPeripheryMaskROMSlave
+    with HasPeripheryDebug
+    with HasSystemErrorSlave
+    with HasPeripheryUART
+    with HasPeripheryTerminal
+    with HasPeripherySPI
+    with HasPeripheryGPIO
+    with HasMemoryML507 {
+  override lazy val module = new U500ML507DevKitSystemModule(this)
+}
+
+class U500ML507DevKitSystemModule[+L <: U500ML507DevKitSystem](_outer: L)
+  extends RocketSubsystemModuleImp(_outer)
+    with HasRTCModuleImp
+    with HasPeripheryDebugModuleImp
+    with HasPeripheryUARTModuleImp
+    with HasPeripheryTerminalModuleImp
+    with HasPeripherySPIModuleImp
+    with HasPeripheryGPIOModuleImp
+    with HasMemoryML507ModuleImp {
+  // Reset vector is set to the location of the mask rom
+  val maskROMParams = p(PeripheryMaskROMKey)
+  global_reset_vector := maskROMParams(0).address.U
+}