Wesley W. Terpstra
|
4386187016
|
vc707: add clock groups dynamically iff they exist
|
2018-02-25 14:33:32 -08:00 |
|
Wesley W. Terpstra
|
8519ba8d4e
|
vc707: setup 100MHz PLL
|
2018-02-08 07:21:45 -08:00 |
|
Wesley W. Terpstra
|
506d2da883
|
vc707: update constraints to match correct mmcm
|
2018-02-08 07:21:45 -08:00 |
|
Henry Styles
|
045b290fbd
|
VC707 JTAG support throught XM105 FMC or reuse of LCD header
|
2018-02-08 07:21:44 -08:00 |
|
Henry Styles
|
e1bfb75188
|
VC707 Shell : Make DDR and PCIe optional, mixed into Shell with traits. Also add MMCM to provide 65Mhz (and multiples) clock
|
2017-11-01 14:23:07 -07:00 |
|
Henry Styles
|
dc6bb40d1b
|
VC707 : update contraints file to match PCIe and MIG signal names now claimed directly from the IP
|
2017-10-23 17:27:36 -07:00 |
|
Megan Wachs
|
31650a2d23
|
Merge remote-tracking branch 'origin/master' into synchronizers
|
2017-09-07 10:46:03 -07:00 |
|
Henry Styles
|
b7ee0ab0f0
|
fix PCIe vc707 design contraints : PCIe pins and UART RX sync register
|
2017-09-07 10:41:12 -07:00 |
|
Megan Wachs
|
cab572fab2
|
synchronizers: decided that ShiftRegInit should be reversed as the others.
|
2017-09-07 09:54:35 -07:00 |
|
Megan Wachs
|
fd70d118d3
|
synchronizers: Update constraints to match new hierarchy for synchronizers
|
2017-09-07 07:50:22 -07:00 |
|
Shreesha Srinath
|
c58e79f155
|
vc707: Updates to the constraints and shell
|
2017-08-17 18:51:01 -07:00 |
|
Shreesha Srinath
|
ab8cf0775f
|
Initial commit for fpga-shells
|
2017-08-16 11:23:45 -07:00 |
|