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b7ee0ab0f0
fpga-shells/xilinx/vc707/constraints
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Henry Styles b7ee0ab0f0 fix PCIe vc707 design contraints : PCIe pins and UART RX sync register
2017-09-07 10:41:12 -07:00
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vc707-master.xdc fix PCIe vc707 design contraints : PCIe pins and UART RX sync register 2017-09-07 10:41:12 -07:00