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77694a6741
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Add clock generation for the mig
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2018-05-10 01:04:52 +02:00 |
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5bcc4e82fd
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Generate separate processor and terminal clocks
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2018-04-30 22:52:02 +02:00 |
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8329b232e2
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Hold ml507 in reset while clock not locked
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2018-04-19 01:25:31 +02:00 |
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e9625bf8ee
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Add initial ML507Shell stub based on VC707Shell
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2018-04-12 00:42:46 +02:00 |
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Wesley W. Terpstra
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8519ba8d4e
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vc707: setup 100MHz PLL
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2018-02-08 07:21:45 -08:00 |
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Wesley W. Terpstra
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9c38f20333
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vc707 axi: move addresses to line up with ChipLink
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2018-02-08 07:21:44 -08:00 |
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Henry Styles
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61ece0bf00
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VC707 Shell : additional skewed clocks
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2018-02-08 07:21:44 -08:00 |
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Henry Styles
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f9dc552ddc
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Xilinx unisim typo
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2018-02-08 07:21:44 -08:00 |
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Henry Styles
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33c88b8cc4
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Move Xilinx unisims into separate file
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2018-02-08 07:21:44 -08:00 |
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Wesley W. Terpstra
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8b0d7ec91a
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TransferSizes: just because a device CAN do more does not mean it should (#15)
Capping TransferSizes at 128 fits nicely in 3 size bits.
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2017-12-10 00:42:11 -08:00 |
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Henry Styles
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e1bfb75188
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VC707 Shell : Make DDR and PCIe optional, mixed into Shell with traits. Also add MMCM to provide 65Mhz (and multiples) clock
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2017-11-01 14:23:07 -07:00 |
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Wesley W. Terpstra
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65ac5d4588
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xilinxVC707mig: convert to the island pattern (#12)
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2017-10-26 16:38:52 -07:00 |
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Wesley W. Terpstra
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4af0552374
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diplomacy: update to new API (#7)
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2017-09-27 16:32:43 -07:00 |
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Henry Styles
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9f75e6eb59
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Support both 4G and 1GB DIMM configuration for VC707
Generate IP TCL and MIG projects from the Chisel blackboxes
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2017-09-08 15:52:53 -07:00 |
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Shreesha Srinath
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ab8cf0775f
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Initial commit for fpga-shells
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2017-08-16 11:23:45 -07:00 |
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