- Böblingen
- https://klemens.schoelhorn.eu
- Joined on
2018-02-28
2ff28e6af6
Add status indication led for the reset button
41362a1cb5
Remove unused UART signals (rs and cs) from ml507
54e61b527c
Disable JTAG support for now
48f3a7e590
Reduce rocket to a single core
7449f52b9a
Update to latest ml507 shell
9afecc1695
Switch to the new ML507Shell
8e4eaf6603
Add TLMemoryML507 stub and integration
0134a8f4dc
Remove vc707 memory interface from ml507
9d02f530fc
vc707shell: work-around too many '++'s => stack overflow issue
080119ec7a
chiplink: add pinout (#20)
0ca9f2bb66
periphery: bus api update (#17)
1dda525578
prologue: support the absence of an xdc/tcl constraint file
6df6db25de
Merge pull request #18 from sifive/dynamic-clock-groups
e9625bf8ee
Add initial ML507Shell stub based on VC707Shell
9d02f530fc
vc707shell: work-around too many '++'s => stack overflow issue
080119ec7a
chiplink: add pinout (#20)
0ca9f2bb66
periphery: bus api update (#17)
1dda525578
prologue: support the absence of an xdc/tcl constraint file
cd9a525a66
Merge pull request #50 from sifive/update_readme_vc707_vivado2016dot4
0e77cb9d87
U500 VC707 FPGA Dev Kit : update required Vivado version from 2016.1 to 2016.4 to fix synthesis bug effecting debug module
c0a2869e56
Merge pull request #49 from sifive/update_vc707_sdboot
0663bb7627
Correct GPIO/SPI/UART base addresse for vc707 sdboot
fff18810cd
Merge pull request #48 from sifive/chiplink
cd9a525a66
Merge pull request #50 from sifive/update_readme_vc707_vivado2016dot4
0e77cb9d87
U500 VC707 FPGA Dev Kit : update required Vivado version from 2016.1 to 2016.4 to fix synthesis bug effecting debug module
c0a2869e56
Merge pull request #49 from sifive/update_vc707_sdboot
0663bb7627
Correct GPIO/SPI/UART base addresse for vc707 sdboot
fff18810cd
Merge pull request #48 from sifive/chiplink
5fdadd244c
Add makefile and config for the ml507 board
cd9a525a66
Merge pull request #50 from sifive/update_readme_vc707_vivado2016dot4
0e77cb9d87
U500 VC707 FPGA Dev Kit : update required Vivado version from 2016.1 to 2016.4 to fix synthesis bug effecting debug module
c0a2869e56
Merge pull request #49 from sifive/update_vc707_sdboot
0663bb7627
Correct GPIO/SPI/UART base addresse for vc707 sdboot
9b3763ea92
Merge pull request #47 from sifive/bump-repos
1445a381a1
platforms: fixup to new package names
6c9b159659
submodules: bump again for the latest refactor
c076d53fe9
fpga-shells: bump to fix timing closure
756e2e82a1
build: update all submodules to their current master
a0edbba645
Remove PCIe
9b3763ea92
Merge pull request #47 from sifive/bump-repos
1445a381a1
platforms: fixup to new package names
6c9b159659
submodules: bump again for the latest refactor
c076d53fe9
fpga-shells: bump to fix timing closure
77b03ae70d
Updated README.md after findings of 2018-03-02.
4a98e876cf
Updated section "code" of README.md
a60e1774ee
Document PIN-order in the README
fe6fe8ea52
Disable led display after 10 seconds to save energy
171c3659f8
Update README
b3b265b45b
improve ASCII-Art
043d021a93
Compile statically and optimize for size
6613661ce4
Improve parsing possibility of program output
306b35f451
add hints for program help.
735ef3ba75
find better description for hints to dependencies.