|
|
180ed8557e
|
Add sd breakout board as submodule
|
2018-06-05 18:04:47 +02:00 |
|
|
|
34f837d7b1
|
Add build instructions and license
|
2018-06-05 18:03:24 +02:00 |
|
|
|
ce76d77699
|
Add missing module to the ISE project and ignore generated MIG-Core
|
2018-06-05 17:15:48 +02:00 |
|
|
|
dfd2d2ac9b
|
Use new ise virtex-6 parser and set SYNTHESIS verilog constant
|
2018-06-05 16:10:42 +02:00 |
|
|
|
fbab58fa13
|
Add constraint files to the ise project
|
2018-06-05 16:04:27 +02:00 |
|
|
|
f9b72609f1
|
Import clock definition files
|
2018-06-05 16:04:27 +02:00 |
|
|
|
ea067af1ac
|
Import main constraints file
|
2018-06-05 16:04:27 +02:00 |
|
|
|
55cd91d4da
|
Add basic ise project with relative paths
|
2018-06-05 16:04:27 +02:00 |
|
|
|
e1bf43fa47
|
Add MIG wrapper and ddr2 constraints
We cannot add the full repository here, because it contains the mig core,
which is not allowed to be redistributed publicy.
|
2018-06-05 16:04:27 +02:00 |
|
|
|
73af9d6711
|
Import terminal as a submodule
|
2018-06-05 15:33:43 +02:00 |
|
|
|
1996a97f65
|
Import freedom repos as submodules
|
2018-06-05 15:11:52 +02:00 |
|
