riscv/sifive-blocks
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43 Commits

Author SHA1 Message Date
Megan Wachs
fb4977b518 SPI: Use the standard synchronizer primitive for the SPI DQ inputs 2018-03-07 09:54:56 -08:00
Henry Cook
6795f40107 spi: SPIParamsBase param needs to be public 2018-03-04 13:26:19 -08:00
Jack Koenig
39287b9215 Remove cloneTypes in favor of autoclonetype (#51) 
* Remove cloneTypes in favor of autoclonetype

* Consistently use private val for autoclonetype
 2018-03-04 10:29:51 -08:00
Henry Cook
00fbfb6dd8
periphery: bus api update (#50) 2018-03-01 01:15:02 -08:00
Wesley W. Terpstra
90e6ea1d2d
devices: switch to using node-style API (#44) 2017-10-28 12:29:31 -07:00
Wesley W. Terpstra
e4960a4e5a sifive-blocks: update to new rocket API (#43) 2017-10-26 16:10:18 -07:00
Wesley W. Terpstra
4fcf349adb diplomacy: update to new API (#40) 2017-09-27 16:33:18 -07:00
Megan Wachs
81e301f9f7 pinctrl: Create extendable Signal classes 2017-09-22 13:17:31 -07:00
Megan Wachs
6a13639cf3 SPI: Make it easier to build arbitrary bundles 2017-09-20 16:21:21 -07:00
Megan Wachs
97c3fcb4b6 shiftregs: Use SyncResetSynchronizerShiftReg primitives where appropriate 2017-09-06 10:59:07 -07:00
Megan Wachs
c68d556768 ShiftRegInit: use the rocket-chip version since it is there now 2017-09-05 17:51:40 -07:00
Megan Wachs
70c25846b8 spi: Make memory mapped interface depth a parameter 2017-08-20 12:39:38 -07:00
Wesley W. Terpstra
a814cba04f spi: put a request buffer infront of SPI 
This will prevent SPI from blocking other pbus requests.
 2017-08-19 12:52:10 -07:00
Albert Ou
c59356d1de spi: Fix invalid D channel response when flash interface is disabled 
Issue: When the memory-mapped flash region is accessed while the flash
read mode is disabled (fctrl.en flag is clear), the SPI flash controller
generates an invalid response on the D channel.
This may cause the TileLink bus to deadlock.

Workaround: Software should avoid accessing the memory-mapped flash
region when the SPI controller is not in the flash read mode.
 2017-08-02 13:50:00 -07:00
Wesley W. Terpstra
fced2323bd spi: remove removed sink arg 2017-07-26 16:02:44 -07:00
Megan Wachs
aa6d911c26 Ports: Rename the 'fromXYZPort' to 'fromPort' since it's redundant 2017-07-25 08:36:28 -07:00
Megan Wachs
0a80d1987d Merge remote-tracking branch 'origin/master' into typed_pad_ctrl 2017-07-24 10:11:52 -07:00
Henry Cook
9ae6413273 periphery: peripherals now in coreplex (#26) 
* periphery: peripherals now in coreplex

* use fromAsyncFIFOMaster
 2017-07-23 08:31:44 -07:00
Megan Wachs
06f0d20742 Add missing cloneType methods to pin bundles 2017-07-20 11:36:31 -07:00
Megan Wachs
ef4f2ed888 Remove pluralization on interface names. Require clocks and resets explicitly when necessary 2017-07-19 14:51:50 -07:00
Megan Wachs
4d74e8f67f Make it possible to adjust the type of pad controls used, 
and seperate out some of the "GPIO Peripheral" from "Pin Control"
 2017-07-19 08:01:42 -07:00
Henry Cook
fb9dd31374 Refactor package hierarchy. (#25) 2017-07-07 10:48:57 -07:00
Wesley W. Terpstra
a8e20f447c spi: include mem region (#23) 2017-06-28 17:46:45 -07:00
Henry Cook
473464eaa9 make some base bundle classes easier to clone (#20) 2017-06-14 19:47:56 -07:00
Wesley W. Terpstra
90d3931f5a spi: add dts ranges field for memory mapped spi (#19) 2017-06-14 17:06:55 -07:00
Megan Wachs
8bfda68858 More Peripheral-to-pins cleanups 2017-06-13 11:00:29 -07:00
Megan Wachs
b06b80dccd GPIO/SPI/I2C: Add sync stages in place of dummy variable since we need them and they are more useful. 2017-06-12 17:53:51 -07:00
Megan Wachs
7c118790cb GPIO/SPI/I2C: Add sync stages in place of dummy variable since we need them and they are more useful. 2017-06-12 17:53:08 -07:00
Henry Cook
d4bb8a77ea periphery: convert periphery bundle traits to work with system-level multi-io module 2017-06-12 16:57:47 -07:00
Megan Wachs
79f64de12c peripheral_options: Actually compiles 2017-06-09 13:53:22 -07:00
Megan Wachs
29226701a8 SPIFlash: make it listable 2017-06-08 16:29:01 -07:00
Albert Ou
75d6a7c6ea spi: Fix off-by-one error in calculating cycles per data frame 
Issue: Configuring the frame length to certain values causes incorrect
operation.

Symptoms: Certain frame lengths result in the master sending one extra
clock pulse.  The slave device may then become desynchronized.

Workaround: The following frame lengths are supported and can be used.
Do not use other frame lengths.
	* Serial mode: 0, 2, 4, 6, 8
	* Dual mode:   0, 1, 3, 5, 7, 8
	* Quad mode:   0, 1, 2, 3, 5, 6, 7, 8
 2017-05-02 12:35:34 -07:00
Albert Ou
eea10f5129 spi: Fix io.port.dq(3) output enable 
Issue: The output enable signal for DQ[3] is not driven properly.

Symptoms: Output data from master to slave is not properly transmitted
in quad mode.  Data received from the slave is unaffected.

Workaround: When interfacing with SPI flash devices, do not use the
"Quad Input/Output Fast Read" command (opcode 0xEB) while in the
Extended SPI protocol.  Do not use the Native Quad SPI protocol.
 2017-05-02 12:07:37 -07:00
Megan Wachs
70ac4044d1 spi: correct polarity of FIRRTL combo loop detection workaround. 2017-03-31 13:49:34 -07:00
Jack Koenig
6a3b5e1a31 "Fix" false combinational loop through SPIArbiter 
Mux1H converts aggregates to UInt, muxes, then converts back which can
look like a cominational loop.
 2017-03-30 19:12:15 -07:00
Yunsup Lee
c1872c574b update TLRegisterNode to take Seq of AddressSet 2017-03-21 22:12:37 -07:00
Wesley W. Terpstra
46aa6b0ac4 devices: include DTS meta-data 2017-03-02 20:39:30 -08:00
Wesley W. Terpstra
baccd5ada2 devices: create periphery keys for all devices 
Standardize how they are connected to the periphery bus
 2017-03-02 20:39:25 -08:00
Megan Wachs
03be9aba67 Use HomogenousBag to handle lists of peripherals 
Previously we had to do weird things to make non-homogenous
lists of items (e.g. PWM Peripherals where ncmp were different from one to
the other) into a vector. But now Chisel supports a Record type,
and we use the HomogenousBag utility to do this more naturally.
This also deletes all the cruft which was introduced to get
around the limitation which doesn't exist anymore.
 2017-02-16 17:52:24 -08:00
Wesley W. Terpstra
c010a1557a sifive-blocks: trust diplomacy to get names right 2017-02-01 13:53:54 -08:00
Wesley W. Terpstra
535be3e976 spi: work around ucb-bar/chisel3#472 2017-01-31 14:03:14 -08:00
Wesley W. Terpstra
45c491cd69 LazyModule: provide Parameters 
This tracks PR #478 in rocketchip.
 2016-12-07 13:21:20 -08:00
SiFive
7916ef5249 Initial commit. 2016-11-29 04:08:44 -08:00