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riscv/sifive-blocks
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6a13639cf3e64acf4a672daa0c895e4919d4a6dc
sifive-blocks/src/main/scala/devices/spi
T
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Megan Wachs 6a13639cf3 SPI: Make it easier to build arbitrary bundles
2017-09-20 16:21:21 -07:00
..
SPIArbiter.scala
spi: correct polarity of FIRRTL combo loop detection workaround.
2017-03-31 13:49:34 -07:00
SPIBundle.scala
Refactor package hierarchy. (#25)
2017-07-07 10:48:57 -07:00
SPIConsts.scala
spi: work around ucb-bar/chisel3#472
2017-01-31 14:03:14 -08:00
SPIFIFO.scala
spi: Fix off-by-one error in calculating cycles per data frame
2017-05-02 12:35:34 -07:00
SPIFlash.scala
spi: Fix invalid D channel response when flash interface is disabled
2017-08-02 13:50:00 -07:00
SPIMedia.scala
devices: create periphery keys for all devices
2017-03-02 20:39:25 -08:00
SPIPeriphery.scala
spi: Make memory mapped interface depth a parameter
2017-08-20 12:39:38 -07:00
SPIPhysical.scala
shiftregs: Use SyncResetSynchronizerShiftReg primitives where appropriate
2017-09-06 10:59:07 -07:00
SPIPins.scala
SPI: Make it easier to build arbitrary bundles
2017-09-20 16:21:21 -07:00
SPIRegs.scala
Initial commit.
2016-11-29 04:08:44 -08:00
TLSPI.scala
Refactor package hierarchy. (#25)
2017-07-07 10:48:57 -07:00
TLSPIFlash.scala
spi: Make memory mapped interface depth a parameter
2017-08-20 12:39:38 -07:00
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