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riscv/sifive-blocks
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aa6d911c265e822bc34f48872838fc3077473f7a
sifive-blocks/src/main/scala/devices/spi
T
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Megan Wachs aa6d911c26 Ports: Rename the 'fromXYZPort' to 'fromPort' since it's redundant
2017-07-25 08:36:28 -07:00
..
SPIArbiter.scala
spi: correct polarity of FIRRTL combo loop detection workaround.
2017-03-31 13:49:34 -07:00
SPIBundle.scala
Refactor package hierarchy. (#25)
2017-07-07 10:48:57 -07:00
SPIConsts.scala
spi: work around ucb-bar/chisel3#472
2017-01-31 14:03:14 -08:00
SPIFIFO.scala
spi: Fix off-by-one error in calculating cycles per data frame
2017-05-02 12:35:34 -07:00
SPIFlash.scala
devices: create periphery keys for all devices
2017-03-02 20:39:25 -08:00
SPIMedia.scala
devices: create periphery keys for all devices
2017-03-02 20:39:25 -08:00
SPIPeriphery.scala
Merge remote-tracking branch 'origin/master' into typed_pad_ctrl
2017-07-24 10:11:52 -07:00
SPIPhysical.scala
spi: Fix io.port.dq(3) output enable
2017-05-02 12:07:37 -07:00
SPIPins.scala
Ports: Rename the 'fromXYZPort' to 'fromPort' since it's redundant
2017-07-25 08:36:28 -07:00
SPIRegs.scala
Initial commit.
2016-11-29 04:08:44 -08:00
TLSPI.scala
Refactor package hierarchy. (#25)
2017-07-07 10:48:57 -07:00
TLSPIFlash.scala
Refactor package hierarchy. (#25)
2017-07-07 10:48:57 -07:00
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