This refactors the receiver logic to compensate for the case of the baud
rate divisor not being multiple of the oversampling period.
Previously, the bit time was effectively rounded to (s * floor(div / s))
cycles, where "s" is the oversampling factor - the number of
intermediate samples for each data bit. The remainder r = (div % s) was
ignored, thereby resulting in gradually accumulated drift that became
significant for divisor values on the same order of magnitude as "s".
The revised approach inserts the required additional delay by extending
the last "r" samples of a given data bit by one cycle each.
Issue: When the memory-mapped flash region is accessed while the flash
read mode is disabled (fctrl.en flag is clear), the SPI flash controller
generates an invalid response on the D channel.
This may cause the TileLink bus to deadlock.
Workaround: Software should avoid accessing the memory-mapped flash
region when the SPI controller is not in the flash read mode.
Issue: Configuring the frame length to certain values causes incorrect
operation.
Symptoms: Certain frame lengths result in the master sending one extra
clock pulse. The slave device may then become desynchronized.
Workaround: The following frame lengths are supported and can be used.
Do not use other frame lengths.
* Serial mode: 0, 2, 4, 6, 8
* Dual mode: 0, 1, 3, 5, 7, 8
* Quad mode: 0, 1, 2, 3, 5, 6, 7, 8
Issue: The output enable signal for DQ[3] is not driven properly.
Symptoms: Output data from master to slave is not properly transmitted
in quad mode. Data received from the slave is unaffected.
Workaround: When interfacing with SPI flash devices, do not use the
"Quad Input/Output Fast Read" command (opcode 0xEB) while in the
Extended SPI protocol. Do not use the Native Quad SPI protocol.
Albert Ou
