Freedom RTL blocks (https://github.com/sifive/sifive-blocks)
c59356d1de
Issue: When the memory-mapped flash region is accessed while the flash read mode is disabled (fctrl.en flag is clear), the SPI flash controller generates an invalid response on the D channel. This may cause the TileLink bus to deadlock. Workaround: Software should avoid accessing the memory-mapped flash region when the SPI controller is not in the flash read mode. |
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src/main/scala | ||
vsrc | ||
.gitignore | ||
LICENSE |