Remove cloneTypes in favor of autoclonetype (#51)

* Remove cloneTypes in favor of autoclonetype

* Consistently use private val for autoclonetype

src/main/scala/devices/gpio/GPIO.scala

@@ -8,7 +8,7 @@ import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.util.SynchronizerShiftReg
 import freechips.rocketchip.regmapper._
 import freechips.rocketchip.tilelink._
-import freechips.rocketchip.util.{AsyncResetRegVec, GenericParameterizedBundle}
+import freechips.rocketchip.util.AsyncResetRegVec
 
 case class GPIOParams(address: BigInt, width: Int, includeIOF: Boolean = false)
 
@@ -75,7 +75,7 @@ object BasePinToIOF {
 // level, and we have to do the pinmux
 // outside of RocketChipTop.
 
-class GPIOPortIO(c: GPIOParams) extends GenericParameterizedBundle(c) {
+class GPIOPortIO(private val c: GPIOParams) extends Bundle {
   val pins = Vec(c.width, new EnhancedPin())
   val iof_0 = if (c.includeIOF) Some(Vec(c.width, new IOFPin).flip) else None
   val iof_1 = if (c.includeIOF) Some(Vec(c.width, new IOFPin).flip) else None

src/main/scala/devices/gpio/GPIOPins.scala

@@ -9,17 +9,11 @@ import sifive.blocks.devices.pinctrl.{Pin}
 // even though it looks like something that more directly talks to
 // a pin. It also makes it possible to change the exact
 // type of pad this connects to.
-class GPIOSignals[T <: Data] (pingen: ()=> T,  c: GPIOParams) extends Bundle {
+class GPIOSignals[T <: Data](private val pingen: () => T, private val c: GPIOParams) extends Bundle {
   val pins = Vec(c.width, pingen())
-
-  override def cloneType: this.type =
-    this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
 }
 
-class GPIOPins[T <: Pin] (pingen: ()=> T,  c: GPIOParams) extends GPIOSignals[T](pingen, c) {
-  override def cloneType: this.type =
-    this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
-}
+class GPIOPins[T <: Pin](pingen: () => T, c: GPIOParams) extends GPIOSignals[T](pingen, c)
 
 object GPIOPinsFromPort {
 

src/main/scala/devices/i2c/I2CPins.scala

@@ -6,13 +6,9 @@ import chisel3.experimental.{withClockAndReset}
 import freechips.rocketchip.util.SyncResetSynchronizerShiftReg
 import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
 
-class I2CSignals[T <: Data](pingen: () => T) extends Bundle {
-
+class I2CSignals[T <: Data](private val pingen: () => T) extends Bundle {
   val scl: T = pingen()
   val sda: T = pingen()
-
-  override def cloneType: this.type =
-    this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
 }
 
 class I2CPins[T <: Pin](pingen: () => T) extends I2CSignals[T](pingen)

src/main/scala/devices/pwm/PWMPeriphery.scala

@@ -10,7 +10,6 @@ import sifive.blocks.devices.pinctrl.{Pin}
 
 class PWMPortIO(val c: PWMParams) extends Bundle {
   val port = Vec(c.ncmp, Bool()).asOutput
-  override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type]
 }
 
 

src/main/scala/devices/pwm/PWMPins.scala

@@ -4,12 +4,8 @@ package sifive.blocks.devices.pwm
 import Chisel._
 import sifive.blocks.devices.pinctrl.{Pin}
 
-class PWMSignals[T <: Data] (pingen: ()=> T, val c: PWMParams) extends Bundle {
-
+class PWMSignals[T <: Data](private val pingen: () => T, val c: PWMParams) extends Bundle {
   val pwm: Vec[T] = Vec(c.ncmp, pingen())
-
-  override def cloneType: this.type =
-    this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
 }
 
 class PWMPins[T <: Pin](pingen: () => T, c: PWMParams) extends PWMSignals[T](pingen, c)

src/main/scala/devices/spi/SPIBundle.scala

@@ -2,12 +2,8 @@
 package sifive.blocks.devices.spi
 
 import Chisel._
-import freechips.rocketchip.util.GenericParameterizedBundle
 
-abstract class SPIBundle(val c: SPIParamsBase) extends GenericParameterizedBundle(c) {
-  override def cloneType: SPIBundle.this.type =
-    this.getClass.getConstructors.head.newInstance(c).asInstanceOf[this.type]
-}
+abstract class SPIBundle(private val c: SPIParamsBase) extends Bundle
 
 class SPIDataIO extends Bundle {
   val i = Bool(INPUT)

src/main/scala/devices/spi/SPIPins.scala

@@ -5,15 +5,11 @@ import Chisel._
 import chisel3.experimental.{withClockAndReset}
 import sifive.blocks.devices.pinctrl.{PinCtrl, Pin}
 
-class SPISignals[T <: Data] (pingen: ()=> T, c: SPIParamsBase) extends SPIBundle(c) {
+class SPISignals[T <: Data](private val pingen: () => T, c: SPIParamsBase) extends SPIBundle(c) {
 
   val sck = pingen()
   val dq  = Vec(4, pingen())
   val cs  = Vec(c.csWidth, pingen())
-
-  override def cloneType: this.type =
-    this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
-
 }
 
 class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPISignals(pingen, c)

src/main/scala/devices/uart/UARTPins.scala

@@ -6,12 +6,9 @@ import chisel3.experimental.{withClockAndReset}
 import freechips.rocketchip.util.SyncResetSynchronizerShiftReg
 import sifive.blocks.devices.pinctrl.{Pin}
 
-class UARTSignals[T <: Data] (pingen: () => T) extends Bundle {
+class UARTSignals[T <: Data](private val pingen: () => T) extends Bundle {
   val rxd = pingen()
   val txd = pingen()
-
-  override def cloneType: this.type =
-    this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
 }
 
 class UARTPins[T <: Pin](pingen: () => T) extends UARTSignals[T](pingen)

src/main/scala/util/Timer.scala

@@ -6,12 +6,10 @@ import Chisel.ImplicitConversions._
 import freechips.rocketchip.regmapper._
 import freechips.rocketchip.util.WideCounter
 
-class SlaveRegIF(w: Int) extends Bundle {
+class SlaveRegIF(private val w: Int) extends Bundle {
   val write = Valid(UInt(width = w)).flip
   val read = UInt(OUTPUT, w)
 
-  override def cloneType: this.type = new SlaveRegIF(w).asInstanceOf[this.type]
-
   def toRegField(dummy: Int = 0): RegField = {
     def writeFn(valid: Bool, data: UInt): Bool = {
       write.valid := valid