42 lines
1.2 KiB
Scala
42 lines
1.2 KiB
Scala
// See LICENSE for license details.
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package sifive.blocks.devices.pwm
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import Chisel._
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import freechips.rocketchip.config.Field
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import freechips.rocketchip.subsystem.BaseSubsystem
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import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
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import freechips.rocketchip.util.HeterogeneousBag
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import sifive.blocks.devices.pinctrl.{Pin}
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class PWMPortIO(val c: PWMParams) extends Bundle {
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val port = Vec(c.ncmp, Bool()).asOutput
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}
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case object PeripheryPWMKey extends Field[Seq[PWMParams]]
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trait HasPeripheryPWM { this: BaseSubsystem =>
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val pwmParams = p(PeripheryPWMKey)
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val pwms = pwmParams.zipWithIndex.map { case(params, i) =>
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val name = Some(s"pwm_$i")
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val pwm = LazyModule(new TLPWM(pbus.beatBytes, params)).suggestName(name)
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pbus.toVariableWidthSlave(name) { pwm.node }
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ibus.fromSync := pwm.intnode
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pwm
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}
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}
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trait HasPeripheryPWMBundle {
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val pwm: HeterogeneousBag[PWMPortIO]
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}
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trait HasPeripheryPWMModuleImp extends LazyModuleImp with HasPeripheryPWMBundle {
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val outer: HasPeripheryPWM
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val pwm = IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_))))
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(pwm zip outer.pwms) foreach { case (io, device) =>
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io.port := device.module.io.gpio
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}
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}
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