32 lines
1.1 KiB
Scala
32 lines
1.1 KiB
Scala
// See LICENSE for license details.
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package sifive.blocks.devices.i2c
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import Chisel._
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import chisel3.experimental.{withClockAndReset}
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import freechips.rocketchip.util.SyncResetSynchronizerShiftReg
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import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
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class I2CSignals[T <: Data](private val pingen: () => T) extends Bundle {
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val scl: T = pingen()
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val sda: T = pingen()
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}
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class I2CPins[T <: Pin](pingen: () => T) extends I2CSignals[T](pingen)
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object I2CPinsFromPort {
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def apply[T <: Pin](pins: I2CSignals[T], i2c: I2CPort, clock: Clock, reset: Bool, syncStages: Int = 0) = {
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withClockAndReset(clock, reset) {
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pins.scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B)
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pins.scl.o.oe := i2c.scl.oe
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i2c.scl.in := SyncResetSynchronizerShiftReg(pins.scl.i.ival, syncStages, init = Bool(true),
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name = Some("i2c_scl_sync"))
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pins.sda.outputPin(i2c.sda.out, pue=true.B, ie = true.B)
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pins.sda.o.oe := i2c.sda.oe
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i2c.sda.in := SyncResetSynchronizerShiftReg(pins.sda.i.ival, syncStages, init = Bool(true),
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name = Some("i2c_sda_sync"))
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}
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}
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}
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