235 lines
7.8 KiB
Scala
235 lines
7.8 KiB
Scala
// See LICENSE for license details.
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package sifive.blocks.devices.gpio
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import Chisel._
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import chisel3.experimental.MultiIOModule
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import sifive.blocks.devices.pinctrl.{PinCtrl, Pin, BasePin, EnhancedPin, EnhancedPinCtrl}
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.util.SynchronizerShiftReg
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import freechips.rocketchip.regmapper._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util.AsyncResetRegVec
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case class GPIOParams(address: BigInt, width: Int, includeIOF: Boolean = false)
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// This is the actual IOF interface.pa
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// Add a valid bit to indicate whether
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// there is something actually connected
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// to this.
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class IOFCtrl extends PinCtrl {
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val valid = Bool()
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}
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// By default,
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object IOFCtrl {
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def apply(): IOFCtrl = {
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val iof = Wire(new IOFCtrl())
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iof.valid := Bool(false)
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iof.oval := Bool(false)
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iof.oe := Bool(false)
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iof.ie := Bool(false)
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iof
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}
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}
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// Package up the inputs and outputs
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// for the IOF
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class IOFPin extends Pin {
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val o = new IOFCtrl().asOutput
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def default(): Unit = {
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this.o.oval := Bool(false)
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this.o.oe := Bool(false)
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this.o.ie := Bool(false)
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this.o.valid := Bool(false)
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}
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def inputPin(pue: Bool = Bool(false) /*ignored*/): Bool = {
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this.o.oval := Bool(false)
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this.o.oe := Bool(false)
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this.o.ie := Bool(true)
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this.i.ival
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}
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def outputPin(signal: Bool,
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pue: Bool = Bool(false), /*ignored*/
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ds: Bool = Bool(false), /*ignored*/
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ie: Bool = Bool(false)
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): Unit = {
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this.o.oval := signal
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this.o.oe := Bool(true)
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this.o.ie := ie
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}
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}
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// Connect both the i and o side of the pin,
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// and drive the valid signal for the IOF.
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object BasePinToIOF {
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def apply(pin: BasePin, iof: IOFPin): Unit = {
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iof <> pin
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iof.o.valid := Bool(true)
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}
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}
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// This is sort of weird because
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// the IOF end up at the RocketChipTop
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// level, and we have to do the pinmux
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// outside of RocketChipTop.
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class GPIOPortIO(private val c: GPIOParams) extends Bundle {
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val pins = Vec(c.width, new EnhancedPin())
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val iof_0 = if (c.includeIOF) Some(Vec(c.width, new IOFPin).flip) else None
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val iof_1 = if (c.includeIOF) Some(Vec(c.width, new IOFPin).flip) else None
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}
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// It would be better if the IOF were here and
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// we could do the pinmux inside.
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trait HasGPIOBundleContents extends Bundle {
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def params: GPIOParams
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val port = new GPIOPortIO(params)
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}
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trait HasGPIOModuleContents extends MultiIOModule with HasRegMap {
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val io: HasGPIOBundleContents
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val params: GPIOParams
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val c = params
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//--------------------------------------------------
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// CSR Declarations
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// -------------------------------------------------
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// SW Control only.
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val portReg = Reg(init = UInt(0, c.width))
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val oeReg = Module(new AsyncResetRegVec(c.width, 0))
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val pueReg = Module(new AsyncResetRegVec(c.width, 0))
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val dsReg = Reg(init = UInt(0, c.width))
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val ieReg = Module(new AsyncResetRegVec(c.width, 0))
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// Synchronize Input to get valueReg
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val inVal = Wire(UInt(0, width=c.width))
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inVal := Vec(io.port.pins.map(_.i.ival)).asUInt
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val inSyncReg = SynchronizerShiftReg(inVal, 3, Some("inSyncReg"))
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val valueReg = Reg(init = UInt(0, c.width), next = inSyncReg)
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// Interrupt Configuration
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val highIeReg = Reg(init = UInt(0, c.width))
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val lowIeReg = Reg(init = UInt(0, c.width))
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val riseIeReg = Reg(init = UInt(0, c.width))
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val fallIeReg = Reg(init = UInt(0, c.width))
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val highIpReg = Reg(init = UInt(0, c.width))
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val lowIpReg = Reg(init = UInt(0, c.width))
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val riseIpReg = Reg(init = UInt(0, c.width))
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val fallIpReg = Reg(init = UInt(0, c.width))
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// HW IO Function
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val iofEnReg = Module(new AsyncResetRegVec(c.width, 0))
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val iofSelReg = Reg(init = UInt(0, c.width))
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// Invert Output
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val xorReg = Reg(init = UInt(0, c.width))
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//--------------------------------------------------
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// CSR Access Logic (most of this section is boilerplate)
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// -------------------------------------------------
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val rise = ~valueReg & inSyncReg;
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val fall = valueReg & ~inSyncReg;
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val iofEnFields = if (c.includeIOF) (Seq(RegField.rwReg(c.width, iofEnReg.io))) else (Seq(RegField(c.width)))
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val iofSelFields = if (c.includeIOF) (Seq(RegField(c.width, iofSelReg))) else (Seq(RegField(c.width)))
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// Note that these are out of order.
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regmap(
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GPIOCtrlRegs.value -> Seq(RegField.r(c.width, valueReg)),
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GPIOCtrlRegs.output_en -> Seq(RegField.rwReg(c.width, oeReg.io)),
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GPIOCtrlRegs.rise_ie -> Seq(RegField(c.width, riseIeReg)),
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GPIOCtrlRegs.rise_ip -> Seq(RegField.w1ToClear(c.width, riseIpReg, rise)),
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GPIOCtrlRegs.fall_ie -> Seq(RegField(c.width, fallIeReg)),
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GPIOCtrlRegs.fall_ip -> Seq(RegField.w1ToClear(c.width, fallIpReg, fall)),
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GPIOCtrlRegs.high_ie -> Seq(RegField(c.width, highIeReg)),
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GPIOCtrlRegs.high_ip -> Seq(RegField.w1ToClear(c.width, highIpReg, valueReg)),
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GPIOCtrlRegs.low_ie -> Seq(RegField(c.width, lowIeReg)),
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GPIOCtrlRegs.low_ip -> Seq(RegField.w1ToClear(c.width,lowIpReg, ~valueReg)),
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GPIOCtrlRegs.port -> Seq(RegField(c.width, portReg)),
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GPIOCtrlRegs.pullup_en -> Seq(RegField.rwReg(c.width, pueReg.io)),
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GPIOCtrlRegs.iof_en -> iofEnFields,
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GPIOCtrlRegs.iof_sel -> iofSelFields,
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GPIOCtrlRegs.drive -> Seq(RegField(c.width, dsReg)),
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GPIOCtrlRegs.input_en -> Seq(RegField.rwReg(c.width, ieReg.io)),
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GPIOCtrlRegs.out_xor -> Seq(RegField(c.width, xorReg))
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)
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//--------------------------------------------------
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// Actual Pinmux
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// -------------------------------------------------
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val swPinCtrl = Wire(Vec(c.width, new EnhancedPinCtrl()))
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// This strips off the valid.
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val iof0Ctrl = Wire(Vec(c.width, new IOFCtrl()))
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val iof1Ctrl = Wire(Vec(c.width, new IOFCtrl()))
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val iofCtrl = Wire(Vec(c.width, new IOFCtrl()))
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val iofPlusSwPinCtrl = Wire(Vec(c.width, new EnhancedPinCtrl()))
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for (pin <- 0 until c.width) {
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// Software Pin Control
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swPinCtrl(pin).pue := pueReg.io.q(pin)
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swPinCtrl(pin).oval := portReg(pin)
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swPinCtrl(pin).oe := oeReg.io.q(pin)
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swPinCtrl(pin).ds := dsReg(pin)
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swPinCtrl(pin).ie := ieReg.io.q(pin)
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val pre_xor = Wire(new EnhancedPinCtrl())
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if (c.includeIOF) {
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// Allow SW Override for invalid inputs.
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iof0Ctrl(pin) <> swPinCtrl(pin)
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when (io.port.iof_0.get(pin).o.valid) {
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iof0Ctrl(pin) <> io.port.iof_0.get(pin).o
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}
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iof1Ctrl(pin) <> swPinCtrl(pin)
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when (io.port.iof_1.get(pin).o.valid) {
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iof1Ctrl(pin) <> io.port.iof_1.get(pin).o
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}
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// Select IOF 0 vs. IOF 1.
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iofCtrl(pin) <> Mux(iofSelReg(pin), iof1Ctrl(pin), iof0Ctrl(pin))
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// Allow SW Override for things IOF doesn't control.
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iofPlusSwPinCtrl(pin) <> swPinCtrl(pin)
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iofPlusSwPinCtrl(pin) <> iofCtrl(pin)
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// Final XOR & Pin Control
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pre_xor := Mux(iofEnReg.io.q(pin), iofPlusSwPinCtrl(pin), swPinCtrl(pin))
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} else {
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pre_xor := swPinCtrl(pin)
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}
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io.port.pins(pin).o := pre_xor
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io.port.pins(pin).o.oval := pre_xor.oval ^ xorReg(pin)
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// Generate Interrupts
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interrupts(pin) := (riseIpReg(pin) & riseIeReg(pin)) |
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(fallIpReg(pin) & fallIeReg(pin)) |
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(highIpReg(pin) & highIeReg(pin)) |
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(lowIpReg(pin) & lowIeReg(pin))
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if (c.includeIOF) {
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// Send Value to all consumers
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io.port.iof_0.get(pin).i.ival := inSyncReg(pin)
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io.port.iof_1.get(pin).i.ival := inSyncReg(pin)
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}
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}
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}
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// Magic TL2 Incantation to create a TL2 Slave
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class TLGPIO(w: Int, c: GPIOParams)(implicit p: Parameters)
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extends TLRegisterRouter(c.address, "gpio", Seq("sifive,gpio0"), interrupts = c.width, beatBytes = w)(
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new TLRegBundle(c, _) with HasGPIOBundleContents)(
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new TLRegModule(c, _, _) with HasGPIOModuleContents)
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