26 lines
815 B
Scala
26 lines
815 B
Scala
// See LICENSE for license details.
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package sifive.blocks.devices.uart
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import Chisel._
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import chisel3.experimental.{withClockAndReset}
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import freechips.rocketchip.util.SyncResetSynchronizerShiftReg
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import sifive.blocks.devices.pinctrl.{Pin}
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class UARTSignals[T <: Data](private val pingen: () => T) extends Bundle {
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val rxd = pingen()
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val txd = pingen()
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}
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class UARTPins[T <: Pin](pingen: () => T) extends UARTSignals[T](pingen)
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object UARTPinsFromPort {
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def apply[T <: Pin](pins: UARTSignals[T], uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) {
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withClockAndReset(clock, reset) {
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pins.txd.outputPin(uart.txd)
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val rxd_t = pins.rxd.inputPin()
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uart.rxd := SyncResetSynchronizerShiftReg(rxd_t, syncStages, init = Bool(true), name = Some("uart_rxd_sync"))
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}
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}
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}
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