Howard Mao f26c422544 assert that TileLink router has valid route

2016-05-03 12:18:06 -07:00

..

amoalu.scala

Extend AMOALU to support RV32

2016-03-10 17:32:23 -08:00

bram.scala

Add TileLink BRAM slave

2016-04-29 14:10:44 -07:00

broadcast.scala

fix BroadcastHub allocation and routing

2016-04-05 16:21:18 -07:00

cache.scala

don't add pending reads if data is already available

2016-04-06 15:43:21 -07:00

coherence.scala

fix more Chisel3 deprecations

2016-01-14 14:55:45 -08:00

consts.scala

Let isRead be true for store-conditional

2015-09-25 15:28:02 -07:00

converters.scala

Simplify TileLink Narrower

2016-04-26 16:44:54 -07:00

directory.scala

First pages commit

2015-04-29 13:18:26 -07:00

dma.scala

make sure CSR width is parameterizable

2016-02-02 12:49:58 -08:00

ecc.scala

Chisel3 compatibility: use >>Int instead of >>UInt

2015-08-04 13:15:17 -07:00

htif.scala

Take a stab at the PRCI-Rocket interface

2016-05-02 15:20:33 -07:00

interconnect.scala

assert that TileLink router has valid route

2016-05-03 12:18:06 -07:00

metadata.scala

Refactor L2 transaction trackers to each be capable of processing Voluntary Writebacks.

2016-03-10 17:14:34 -08:00

network.scala

Improve simulation speed of BasicCrossbar

2016-04-01 13:28:11 -07:00

package.scala

First pages commit

2015-04-29 13:18:26 -07:00

prci.scala

Add trivial version of PRCI block

2016-05-02 17:49:10 -07:00

rom.scala

Support both Get and GetBlock on ROMSlave

2016-04-30 17:34:12 -07:00

rtc.scala

Add new RTC as TileLink slave, not AXI master

2016-04-27 11:55:35 -07:00

scr.scala

print the base address of each SCR as indicated

2016-04-28 16:31:56 +01:00

tilelink.scala

use manager_id instead of client_id in GrantFromSrc and FinishToDst

2016-04-07 11:20:16 -07:00

uncore.scala

fix BroadcastHub allocation and routing

2016-04-05 16:21:18 -07:00

util.scala

Chisel3 compatibility fix

2016-03-10 17:32:23 -08:00