| .. |
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arbiter.scala
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Added UncachedTileLinkIO port to RocketTile, simplify arbitration
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2015-03-12 16:30:04 -07:00 |
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btb.scala
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Rename some params, use refactored TileLink
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2015-02-01 20:37:31 -08:00 |
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consts.scala
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Renamed PCR to CSR
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2015-04-11 02:16:44 -07:00 |
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core.scala
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Integrate divide/sqrt unit
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2015-04-04 16:39:17 -07:00 |
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csr.scala
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Removed unnecessary signal in CSRIO
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2015-04-11 02:20:34 -07:00 |
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ctrl.scala
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Rename dmem.sret signal to more accurate invalidate_lr
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2015-04-11 02:26:33 -07:00 |
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decode.scala
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fix decodelogic bug for bitwidths >= 64 s/1L/BigInt(1)/
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2015-03-10 10:28:05 -07:00 |
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dpath_alu.scala
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Rename some params, use refactored TileLink
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2015-02-01 20:37:31 -08:00 |
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dpath.scala
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Renamed PCR to CSR
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2015-04-11 02:16:44 -07:00 |
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ecc.scala
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add LICENSE
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2014-09-12 18:06:41 -07:00 |
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fpu.scala
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Integrate divide/sqrt unit
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2015-04-04 16:39:17 -07:00 |
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icache.scala
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Fixed front-end to support four-wide fetch.
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2015-04-10 17:53:47 -07:00 |
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instructions.scala
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Merge [shm]call into ecall, [shm]ret into eret
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2015-03-17 02:24:41 -07:00 |
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multiplier.scala
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Rename some params, use refactored TileLink
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2015-02-01 20:37:31 -08:00 |
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nbdcache.scala
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Rename dmem.sret signal to more accurate invalidate_lr
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2015-04-11 02:26:33 -07:00 |
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package.scala
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New privileged ISA implementation
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2015-03-14 02:49:07 -07:00 |
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ptw.scala
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Update PTE format to reflect reserved bits
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2015-04-04 15:19:15 -07:00 |
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rocc.scala
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Rename dmem.sret signal to more accurate invalidate_lr
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2015-04-11 02:26:33 -07:00 |
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tile.scala
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Rename dmem.sret signal to more accurate invalidate_lr
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2015-04-11 02:26:33 -07:00 |
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tlb.scala
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New virtual memory implementation (Sv39)
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2015-03-27 16:20:59 -07:00 |
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util.scala
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multibeat TL; passes all tests
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2014-12-12 16:54:33 -08:00 |
