Christopher Celio a564f08702 Rename dmem.sret signal to more accurate invalidate_lr

2015-04-11 02:26:33 -07:00

..

arbiter.scala

Added UncachedTileLinkIO port to RocketTile, simplify arbitration

2015-03-12 16:30:04 -07:00

btb.scala

Rename some params, use refactored TileLink

2015-02-01 20:37:31 -08:00

consts.scala

Renamed PCR to CSR

2015-04-11 02:16:44 -07:00

core.scala

Integrate divide/sqrt unit

2015-04-04 16:39:17 -07:00

csr.scala

Removed unnecessary signal in CSRIO

2015-04-11 02:20:34 -07:00

ctrl.scala

Rename dmem.sret signal to more accurate invalidate_lr

2015-04-11 02:26:33 -07:00

decode.scala

fix decodelogic bug for bitwidths >= 64 s/1L/BigInt(1)/

2015-03-10 10:28:05 -07:00

dpath_alu.scala

Rename some params, use refactored TileLink

2015-02-01 20:37:31 -08:00

dpath.scala

Renamed PCR to CSR

2015-04-11 02:16:44 -07:00

ecc.scala

add LICENSE

2014-09-12 18:06:41 -07:00

fpu.scala

Integrate divide/sqrt unit

2015-04-04 16:39:17 -07:00

icache.scala

Fixed front-end to support four-wide fetch.

2015-04-10 17:53:47 -07:00

instructions.scala

Merge [shm]call into ecall, [shm]ret into eret

2015-03-17 02:24:41 -07:00

multiplier.scala

Rename some params, use refactored TileLink

2015-02-01 20:37:31 -08:00

nbdcache.scala

Rename dmem.sret signal to more accurate invalidate_lr

2015-04-11 02:26:33 -07:00

package.scala

New privileged ISA implementation

2015-03-14 02:49:07 -07:00

ptw.scala

Update PTE format to reflect reserved bits

2015-04-04 15:19:15 -07:00

rocc.scala

Rename dmem.sret signal to more accurate invalidate_lr

2015-04-11 02:26:33 -07:00

tile.scala

Rename dmem.sret signal to more accurate invalidate_lr

2015-04-11 02:26:33 -07:00

tlb.scala

New virtual memory implementation (Sv39)

2015-03-27 16:20:59 -07:00

util.scala

multibeat TL; passes all tests

2014-12-12 16:54:33 -08:00