1
0
rocket-chip/rocket/src/main/scala
2015-04-02 01:30:11 -07:00
..
arbiter.scala Added UncachedTileLinkIO port to RocketTile, simplify arbitration 2015-03-12 16:30:04 -07:00
btb.scala Rename some params, use refactored TileLink 2015-02-01 20:37:31 -08:00
consts.scala New privileged ISA implementation 2015-03-14 02:49:07 -07:00
core.scala Add fpu port to the rocc interface 2015-04-02 01:30:11 -07:00
csr.scala Mask off LSBs of sepc/mepc/stvec 2015-03-25 00:20:58 -07:00
ctrl.scala fix rocc exception/s bit 2015-03-17 05:08:23 -07:00
decode.scala fix decodelogic bug for bitwidths >= 64 s/1L/BigInt(1)/ 2015-03-10 10:28:05 -07:00
dpath_alu.scala Rename some params, use refactored TileLink 2015-02-01 20:37:31 -08:00
dpath.scala Hard-wire LSB of JALR to 0, as sent to BTB 2015-03-21 00:16:34 -07:00
ecc.scala add LICENSE 2014-09-12 18:06:41 -07:00
fpu.scala Add fpu port to the rocc interface 2015-04-02 01:30:11 -07:00
icache.scala Misaligned fetches can't happen at the I$ anymore 2015-03-24 23:55:43 -07:00
instructions.scala Merge [shm]call into ecall, [shm]ret into eret 2015-03-17 02:24:41 -07:00
multiplier.scala Rename some params, use refactored TileLink 2015-02-01 20:37:31 -08:00
nbdcache.scala fix long-standing dcache bug 2015-03-17 21:45:17 -07:00
package.scala New privileged ISA implementation 2015-03-14 02:49:07 -07:00
ptw.scala New virtual memory implementation (Sv39) 2015-03-27 16:20:59 -07:00
rocc.scala Add fpu port to the rocc interface 2015-04-02 01:30:11 -07:00
tile.scala uncached port should be a HeaderlessUncachedTileLinkIO type 2015-03-13 02:12:23 -07:00
tlb.scala New virtual memory implementation (Sv39) 2015-03-27 16:20:59 -07:00
util.scala multibeat TL; passes all tests 2014-12-12 16:54:33 -08:00