| .. |
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amoalu.scala
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Extend AMOALU to support RV32
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2016-03-10 17:32:23 -08:00 |
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broadcast.scala
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BroadcastHub race on allocating VolWBs vs Acquires
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2016-03-17 18:32:35 -07:00 |
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cache.scala
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fix addPendingBitWhenPartialWritemask
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2016-03-24 20:01:50 -07:00 |
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coherence.scala
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fix more Chisel3 deprecations
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2016-01-14 14:55:45 -08:00 |
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consts.scala
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Let isRead be true for store-conditional
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2015-09-25 15:28:02 -07:00 |
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converters.scala
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git rid of reorder queue in narrower
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2016-03-24 20:01:50 -07:00 |
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directory.scala
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First pages commit
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2015-04-29 13:18:26 -07:00 |
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dma.scala
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make sure CSR width is parameterizable
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2016-02-02 12:49:58 -08:00 |
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ecc.scala
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Chisel3 compatibility: use >>Int instead of >>UInt
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2015-08-04 13:15:17 -07:00 |
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htif.scala
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Add cloneType methods for Chisel3
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2016-03-21 13:35:02 -07:00 |
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metadata.scala
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Refactor L2 transaction trackers to each be capable of processing Voluntary Writebacks.
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2016-03-10 17:14:34 -08:00 |
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NastiROM.scala
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Fix width of NastiROM rows, preventing out-of-range extraction
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2016-03-03 16:57:16 -08:00 |
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network.scala
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fix more Chisel3 deprecations
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2016-01-14 14:55:45 -08:00 |
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package.scala
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First pages commit
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2015-04-29 13:18:26 -07:00 |
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rtc.scala
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switch RTC to use TileLink instead of AXI
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2016-03-28 12:23:16 -07:00 |
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scr.scala
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Fix the SCR file for Chisel 3
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2016-03-21 11:55:18 -07:00 |
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tilelink.scala
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Avoid right-shift by larger that the bit width
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2016-03-10 17:37:40 -08:00 |
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uncore.scala
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Refactor L2 transaction trackers to each be capable of processing Voluntary Writebacks.
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2016-03-10 17:14:34 -08:00 |
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util.scala
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Chisel3 compatibility fix
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2016-03-10 17:32:23 -08:00 |
