Howard Mao 8e7f18084b switch RTC to use TileLink instead of AXI

2016-03-28 12:23:16 -07:00

..

amoalu.scala

Extend AMOALU to support RV32

2016-03-10 17:32:23 -08:00

broadcast.scala

BroadcastHub race on allocating VolWBs vs Acquires

2016-03-17 18:32:35 -07:00

cache.scala

fix addPendingBitWhenPartialWritemask

2016-03-24 20:01:50 -07:00

coherence.scala

fix more Chisel3 deprecations

2016-01-14 14:55:45 -08:00

consts.scala

Let isRead be true for store-conditional

2015-09-25 15:28:02 -07:00

converters.scala

git rid of reorder queue in narrower

2016-03-24 20:01:50 -07:00

directory.scala

First pages commit

2015-04-29 13:18:26 -07:00

dma.scala

make sure CSR width is parameterizable

2016-02-02 12:49:58 -08:00

ecc.scala

Chisel3 compatibility: use >>Int instead of >>UInt

2015-08-04 13:15:17 -07:00

htif.scala

Add cloneType methods for Chisel3

2016-03-21 13:35:02 -07:00

metadata.scala

Refactor L2 transaction trackers to each be capable of processing Voluntary Writebacks.

2016-03-10 17:14:34 -08:00

NastiROM.scala

Fix width of NastiROM rows, preventing out-of-range extraction

2016-03-03 16:57:16 -08:00

network.scala

fix more Chisel3 deprecations

2016-01-14 14:55:45 -08:00

package.scala

First pages commit

2015-04-29 13:18:26 -07:00

rtc.scala

switch RTC to use TileLink instead of AXI

2016-03-28 12:23:16 -07:00

scr.scala

Fix the SCR file for Chisel 3

2016-03-21 11:55:18 -07:00

tilelink.scala

Avoid right-shift by larger that the bit width

2016-03-10 17:37:40 -08:00

uncore.scala

Refactor L2 transaction trackers to each be capable of processing Voluntary Writebacks.

2016-03-10 17:14:34 -08:00

util.scala

Chisel3 compatibility fix

2016-03-10 17:32:23 -08:00