Andrew Waterman 6134384da4 Fix deprecation warnings

2016-09-16 14:24:19 -07:00

..

AddressDecoder.scala

tilelink2: compute minimal decisive mask

2016-09-15 21:28:56 -07:00

Buffer.scala

tilelink2: add a clock crossing adapter

2016-09-13 18:33:56 -07:00

Bundles.scala

[tilelink2] Convert TileLink2 to use IrrevocableIO. Add checks to the Monitor to enforce Irrevocable semantics on TLEdges. Update the RegisterRouterTests to pass the new Monitor assertions.

2016-09-14 17:43:07 -07:00

Crossing.scala

[tilelink2] Convert TileLink2 to use IrrevocableIO. Add checks to the Monitor to enforce Irrevocable semantics on TLEdges. Update the RegisterRouterTests to pass the new Monitor assertions.

2016-09-14 17:43:07 -07:00

Edges.scala

tilelink2 HintHandler: fill in correct sink in responses

2016-09-12 17:26:40 -07:00

Example.scala

Merge remote-tracking branch 'origin/master' into black_box_regs

2016-09-09 13:12:52 -07:00

Fragmenter.scala

tilelink2: handle bus width=1

2016-09-15 22:15:11 -07:00

Fuzzer.scala

First cut at refactoring unittests into a top-level utility. Individual tests co-located with their DUT. No functional changes.

2016-09-13 20:30:14 -07:00

HintHandler.scala

HintHandler: don't violate Irrevocable rules

2016-09-15 21:28:56 -07:00

IntNodes.scala

tilelink2 IntNodes: record interrupt ranges in parameters

2016-09-08 18:51:43 -07:00

LazyModule.scala

tilelink2: get rid of fragile implicit lazyModule pattern, and support :=

2016-09-08 23:06:59 -07:00

Legacy.scala

testconfigs: disable atomics until AtomicAbsorber finished

2016-09-15 21:28:56 -07:00

Monitor.scala

Fix deprecation warnings

2016-09-16 14:24:19 -07:00

Nodes.scala

tilelink2: allow := on nodes outside the tilelink2 package

2016-09-15 21:28:55 -07:00

package.scala

tilelink2 Node: make it possible for {Identity,Output,Input}Node to pass a Vec

2016-09-08 21:34:20 -07:00

Parameters.scala

tilelink2: compute minimal decisive mask

2016-09-15 21:28:56 -07:00

RAMModel.scala

tilelink2 RAMModel: fix put, get, putAck, getAck case (#282)

2016-09-13 15:44:36 -07:00

RegField.scala

tilelink2: RegField splits up big registers

2016-09-15 21:28:56 -07:00

RegisterCrossing.scala

Merge branch 'master' of github.com:ucb-bar/rocket-chip into tl2-irrevocable

2016-09-14 17:50:17 -07:00

RegisterRouter.scala

tilelink2: handle bus width=1

2016-09-15 22:15:11 -07:00

RegisterRouterTest.scala

tilelink2 RegisterRouterTest: stall on both edges

2016-09-14 18:22:12 -07:00

RegMapper.scala

RegisterRouter: compress register mapping for sparse devices

2016-09-15 21:28:56 -07:00

SRAM.scala

tilelink2: add an executable manager parameter

2016-09-15 21:28:55 -07:00

TLNodes.scala

[tilelink2] Monitor: simplify monitor interface. EdgeIn and EdgeOut are required to be the same, so why pass around both?

2016-09-14 14:23:23 -07:00

WidthWidget.scala

[tilelink2] Convert TileLink2 to use IrrevocableIO. Add checks to the Monitor to enforce Irrevocable semantics on TLEdges. Update the RegisterRouterTests to pass the new Monitor assertions.

2016-09-14 17:43:07 -07:00

Xbar.scala

tilelink2: refactor address into addr_hi on ABC and addr_lo on CD

2016-09-06 23:46:44 -07:00